Inmos Limited

David R Wooten

Sargent S Eaton, Jr

A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.

MOS Capacitive bootstrapping trigger circuit for a clock generator

A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. In the preferred embodiment, the RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, a store for a defective column address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer. When the comparator senses a match, a control signal is generated to initiate substitution of spare memory cells for the defective main memory cells.

Redundancy scheme for a dynamic RAM

A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transistors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/output buss lines. After the logic state is read, the selecting circuit enables the memory cell capacitor to be refreshed for further sensing by the sense amplifier.

Folded bit line-shared sense amplifiers

A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

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Colorado Springs, CO, United States of America

David R Wooten