Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

David R Wooten

Michael F Angelo

Craig A Miller

David E Murray

Kevin B Leigh

Christopher E Simonich

Robert Brett Costley

Sompong Paul Olarig

Gary W Thome

Michael David Johas Teener

Kenneth A Jansen

Randall L Hess

Paul A Santeler

John A Landry

Jeff W Wolford

Christopher C Wanner

Keith Lutsch

Lee B Hinkle

Dan J Driscoll

Carol Erickson

Guy McSwain

A computer system has a USB bus to which one or more USB-compatible devices can connect. One or more of the USB devices has an electrical interface that includes two transmitters and, if desired, a receiver for bidirectional data transmission. The transmitters preferably are dual output, differential transmitters. The transmitters include a slower transmitter and a faster transmitter. The faster transmitter can transmit data at a rate that is faster than the slower transmitter. The electrical interface also includes an electrical termination device that is disposed between the output terminals of the two transmitters. The termination device preferably comprises a pair of multi-purpose termination resistors that can provide serial termination or parallel termination depending whether the fast or slow transmitter is used. When transmitting using the slower transmitter, the receiving USB device disables all of its transmitters and the transmitting USB device disables the output of the faster transmitter by deasserting an output enable (OE) signal to the faster transmitter. The termination device provides serial termination and the data from the slower transmitter passes through the termination device. When transmitting using the faster transmitter, both receiving and transmitting USB devices assert single ended zero (SE ) signals to their slower transmitters which forces both of the slower transmitters' output signals to a low impedance state. In this latter transmission mode, the termination device provides parallel termination, effectively functioning as a &ldquo;pull-down&rdquo; terminator. With parallel termination, echoes effectively are reduced or eliminated and faster data rates are thereby attainable than are generally possible with serially-terminated transmission lines.

Dual mode differential transceiver for a universal serial bus

A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a &ldquo;None_odd&rdquo; message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a &ldquo;None_even&rdquo; message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.

Dual phase arbitration on a bus

A self-orienting logo assembly so that the logo is always in a horizontal orientation. In the preferred embodiments the logo is located on a disk. The disk is weighted or otherwise designed to have its weight distributed nonuniformly. The disk is located inside a housing. The housing is attached to the computer or other equipment bearing the logo. When the housing is located in a vertical plane the disk rotates to allow the logo to remain horizontal. The disk can be rotationally mounted to the housing or can be suspended in liquid. In an alternate embodiment the disk can have a magnet incorporated so that when the disk is in a horizontal orientation it can act as a compass. In another embodiment a portion of the disk is removed and the housing contains an additional logo or wording. The rotation of the disk can then cover or expose the additional logo or wording.

Self-orienting logo assembly

Information is sent on a pair of conductors by sending some of the information by driving the pair of conductors in accordance with a primary signaling character set having two distinct information-carrying characters, and sending other information by driving the pair of conductors in accordance with a third distinct information-carrying character represented by a predefined state of the pair of conductors.

Asynchronous differential communication

A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.

Linked lists of transfer descriptors scheduled at intervals

A secure start-up system for a computer enables a flash memory to be reset in a secured way. Various operations are carried out to make sure that the reset is an authorized one, and to avoid unauthorized, e.g. virus, infiltration. These operations include multiple tests to avoid the probability of the reset being unauthorized. Any one or more than one of the following can be used. Flashing is only authorized when a special flash enable bit is set in the non-volatile memory. This flash enable bit is reset during every startup cycle. Flashing is only authorized from a cold boot as opposed from a warm boot. This minimizes the possibility of a computer routine authorizing flashing by a software reset. Flashing is only authorized from a floppy. This prevents a virus from writing the flashing routine to the boot sector of a non-removable disc. The user is warned prior to flashing, and asked to confirm. Finally, contents of the flashing routine can be checked using some kind of checking algorithm such as a secure hash algorithm.

Secure updating of non-volatile memory

A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.

Low speed serial bus protocol and circuitry

A method and apparatus of synchronizing a serial bus data rate to a serial bus function data rate to eliminate the build up of overruns or underruns of data. A response is provided to a start of frame packet. The response packet contains a response code for indicating a modification to the serial bus frame counter. Thereby, slight variations in data rates can be eliminated by adjusting the serial bus data rate instead of the serial bus function data rate.

Method and apparatus for synchronizing a serial bus clock to a serial

A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligent storage devices and/or controllers, communications devices, video devices and audio devices. The I/O devices perform peer-to-peer message and data transfers, thereby bypassing the operating system running on the computer's CPU. The intelligent I/O devices encrypt messages and data before transmitting them on the I/O bus and conversely decrypt the messages and data upon reception. The encryption provides secrecy and/or authentication of the sender. The devices use keys or passwords to encrypt/decrypt the data. The keys are stored in non-volatile memory in the devices and are distributed to the devices by the system BIOS at initialization time. The devices perform access authorization validation using rule sets also distributed by the BIOS at initialization time. The rule sets specify which I/O operations are valid for a peer I/O device to request of a respective I/O device based, preferably, upon the device class/subclasses of the requesting device. In another embodiment, one of the intelligent I/O devices may be a communications device which serves as a firewall for the I/O bus. In this embodiment, the rule set further includes identification information of the remote machines/devices.

System and method for performing secure device communications in a

A computer system and method for storing data in pages of memory according to a data structure which is stored within the memory and identifies the pages of data. The data structure includes a beginning buffer pointer and an ending buffer pointer. The beginning and ending buffer pointers have page address portions and base address portions. The base address portion of the beginning buffer pointer is changed each time a data location is accessed. The page address portion of the beginning buffer pointer is replaced with the page address portion of the ending buffer pointer when the base address portion of the beginning buffer pointer reaches a page boundary.

Computer system and method for storing data in a buffer which crosses

Method of scheduling interrupts to the linked lists of transfer

A processor having the prior three user addressing modes and a new virtual system mode (VSM). The user modes include real mode, protected mode and virtual 8086 mode. In VSM, the processor can utilize the VSM addressing mechanism and the mode of operation prior to entering VSM. Transitions from the user modes to virtual system mode can be made by indirect calls through a call gate or through vectored entries. While in VSM the processor can utilize VSM memory and I/O space modes, but can also directly utilize the I/O space and memory of the user mode present prior to entry into VSM by using a segment override. The upper 16 MB of the virtual system mode memory space (0xff000000 through 0xffffffff) is designated as non-mapped virtual system mode memory. Virtual system mode logical addresses below 0xff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode). Upon exiting VSM, any processor registers that were saved are restored so the user mode operation can continue as if the emulation operation were performed by the normal interrupt service routine.

System for emulating input/output devices utilizing processor with

A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion logic for passing to the host controller over the serial bus. The host controller includes circuitry for processing the data between the serial bus and a host bus. The host controller further includes 8042 emulation logic for providing a hardware compatible interface to the keyboard controller. The 8042 emulation logic also includes circuitry for communicating over the serial bus during times when the serial bus has not yet been initialized.

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Spring, TX, United States of America

David R Wooten