International Business Machines Corporation

David R Thomas

Jeffrey Haskell Derby

Christopher Dane Jones

John Dennis Zbrozek

Michael Joseph Johnson

Paul W Graf

Stephen F Newton

Donald J Ashley

Jonathan James Hurd

Mark K DeMoor

Paul C Tien

John C Cassani

Elbert A Cheek

A network interface circuit includes an off-hook/on-hook circuit, responsive to the communications network, that provides an off-hook voltage substantially equal to the communications network voltage in an off-hook state and that provides an on-hook voltage in an on-hook state. A voltage controlled current source provides a load current which is proportional to a communications network voltage provided by the communications network. A divider circuit, responsive to the off-hook/on-hook circuit, provides an input voltage and produces an over-voltage, wherein the input voltage is proportional to off-hook or on-hook voltage. A clamping circuit limits the input voltage to one of a first or second predetermined value based on the operating mode and generates a current limited voltage. A control circuit, responsive to the over-voltage and the current-limited voltage and the operating mode and responsive to the off-hook/on-hook circuit, sets the network interface circuit in the off-hook state or the on-hook state based on the input voltage, the current-limited voltage, and the operating mode. Related methods and apparatus are also discussed.

Circuits and methods for improved network interface circuit protection

A communication interface and a design method therefor simultaneously shape a synthesized terminating impedance matching different frequency bands on different connecting communication circuits and a receive path response to prevent frequency roll-off. In some cases, for example based on specified network requirements in a particular country, the terminating impedance presented by the interface must have different frequency characteristics for received signals in different bands of frequencies. A transconductance amplifier and feedback loop provide the terminating impedance for signals received from the communication circuit and serve as a source impedance for signals transmitted by the interface to the telephone line. Signals with different frequencies will generally be received from the telephone line. These different characteristics are realized using different filter networks in the feedback loop. Each network provides a matching terminating impedance to the communication circuit according to the frequency band applied to the circuit. The network shapes the synthesized impedance based upon the relation Z&equals;1/G,H where Z&equals;the terminating impedance; G,is the transconductance of the amplifier and H is the transfer function of the feedback network. For multiple frequencies on the telephone line, multiple networks are included in the feedback loop. Each network is designed to match the impedance requirements of a frequency band without affecting the terminating impedance and frequency band of the other frequency bands. A receive filter circuit is coupled to the feedback loop and in combination with the filter networks in the feedback loop prevent frequency roll-off of received frequencies.

Communication interface having combined shaping of receive response and synthesized matching terminating impedances for different frequency bands and a design method therefor

A communication interface and a design method therefor provide a synthesized terminating impedance matching different frequency bands on a communication circuit. In some cases, for example based on specified network requirements in a particular country, the terminating impedance presented by the interface must have different frequency characteristics for received signals in different bands of frequencies. A transconductance amplifier and feedback loop provide the terminating impedance for signals received from the communication circuit and serves as a source impedance for signals transmitted by the interface to the telephone line. Signals with different frequencies will generally be received from the telephone line. These different characteristics are realized using different filter networks in the feedback loop. Each network provides a matching terminating impedance to the communication circuit according to the frequency band applied to the circuit. The network shapes the synthesized impedance based upon the relation Z&equals;1/G,H where Z&equals;the terminating impedance; G,is the transconductance of the amplifier and H is the transfer function of the feedback network. For multiple frequencies on the telephone line, multiple networks are included in the feedback loop. Each network is designed to match the impedance requirements of a frequency band without affecting the terminating impedance and frequency band of the other frequency bands.

Communication interface having synthesized matching impedances for different frequency bands and a design method therefor

A slope compensation circuit for use with current-programmed switching DC to DC converters is provided which allows operation of the switching converters in the 1-2 MHz range. The circuit avoids feedback of an output voltage which includes the effects of a partially discharged slope capacitor without adding unnecessary delay by using a switch to bypass the discharging slope capacitor and coupling an input stage of the slope compensation circuit to an output driver. A delay in feeding back the output of the slope compensation circuit is provided to assure that the bypassing switch has settled.

High frequency slope compensation circuit for current programmed

A latch (29) is set by a clock (33) to turn on power switch (FET 5). The latch (29) is reset by high voltage comparator (21), by a 50 percent clock delay (35) and by a low-voltage-to-charging-current comparator (19). The voltage at turn-on is compared with a up-ramping reference (15) until it equals an operating reference (17). A temporary delay (pulse circuit 39 and gate 37) is provided before the low voltage comparison can be effective. The delay prevents response to parasitic effects across the power switch (5). Excess drive is prevented resulting from low output currents and malfunctions, and at turn-on.

DC/DC converter

Data from a patch memory (23) is substituted for that in a system ROM (9) by applying high order addresses to a standard PLA (19) having word lines (FIG. 3, 50a-50p). The address orders are separately applied to EXCLUSIVE OR circuits (27a-27g). The PLA (19) is personalized to activate line (21) at addresses to be substituted and to provide logical zeros to the EXCLUSIVE OR circuits (27a-27g) which change during the patch. Only one word line is required for each continuous patch, which vary in size on a patch-by-patch basis. The circuit is fast and efficient. It can be used for a wide variety of memory substitution applications.

Data processing apparatus for address substitution

In response to a periodic pulse on a lead (21) an FET (47) connected gate-to-drain is driven in a low current circuit, producing a threshold potential on node F. This is connected through switch FETs (61) to the word lines (1) of a memory. This holds the gates of memory access switches (5) at threshold. A higher voltage on the bit line (7) takes off charge in memory cells (40) which have drifted from zero charge stored toward the substrate voltage. Absence of the periodic signal activates an FET (59) which grounds node F. High voltage applied to a word line (1) switches off the FET (61) connecting that line to node F.

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Cynthiana, KY, United States of America

David R Thomas