Intel Corporation

David R Smith

Sailesh Bissessur

Mark A Schmisseur

Richard Paul Mackey

Joseph Murray

Jeffrey J McCoskey

Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Method, system, and program for handling Input/Output commands

Method, system, and program for handling input/output commands

Reducing latency and power in the transfer of data between a source and destination domain involves the production of a source-enable signal base on a synchronous-pulse signal. The source-enable signal operates to enable a source register to capture data from a source domain. The source-enable signal may be controlled by a source-inhibit signal. The source-inhibit signal prevents the synchronous-pulse signal from producing the source enable signal and capture clock until data is available for transmission.

Reducing latency and power in asynchronous data transfers

A peripheral component interconnect-extended system that includes a bus bridge. The bus bridge includes an input queue adapted to receive a first request for data from a requesting device coupled to a first bus. The first bus is coupled to the bus bridge, and the first request containing a sequence identification information. The bus bridge also includes a data storage device to contain information to control the bus bridge, and a processor that associates a first unique identification code to the first request.

Use of bus transaction identification codes

Provided are a method, system and article of manufacture for controlling one or more I/O devices coupled to a local bus. A local bus function is associated with the one or more I/O devices. A register corresponding to the local bus function is configured as a memory address. The one or more I/O devices are controlled via the configured register.

Method, system, and program for controlling multiple storage devices

Provided are a method, system, and program for receiving a read request that is one of a plurality of read requests directed toward sequential data and determining whether at least one previous read request for sequential data preceding the data requested by the received read request was not processed. Data is returned to the received read request in response to returning data to the at least one previous read request.

Method, system, and program for returning data to read requests received over a bus

Provided are a method, system, and program for a local bus system. A memory address space in configured to control an I/O device. The memory address space is associated with a port coupled to the local bus system.

Method, system, and program for memory based data transfer

Provided are a method, system, and program that configures an address window of a device controller that communicates with an initiator over a bus, wherein the device controller accesses requests transmitted to one address in the address window on the bus, and configures a maximum number of outstanding read requests the initiator is capable of having to memory addresses in the address window based on a size of the address window.

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Phoenix, AZ, United States of America

David R Smith