Arm Limited

Graphics Properties Holdings, Inc.

Apple Inc.

Silicon Graphics, Incorporated

David R Shreiner

Ian Victor Devereux

Hakan Persson

Alan Commike

Thomas Jeremy Olson

Hansong Zhang

Brad Grantham

Edvard Sørgard

Systems, methods, and computer readable media to implement tessellation edge shaders. Various embodiments receive tessellation patch information that includes patch information and shared edges for the patches. Based on the received patch information, edge tessellation levels for the shared edges may be determined and used to modify edge tessellation levels initially computed for the shared edges. The various embodiments can then generate vertices for a shared edge with the updated edge tessellation levels to adjoin the shared edges without forming cracks. The vertices may be used to render a surface of an object within a digital image or a sequence of digital images.

Tessellation edge shaders

A graphics processing pipeline comprises a tessellation stageoperable to tessellate a patch representing some or all of an object to be rendered, so as to generate positions for a set of vertices for one or more output primitives, and a primitive assembly stageoperable to assemble one or more output primitives for processing using the positions for a set of vertices generated by the tessellation stage and pre-defined information defining the connectivity between at least some of the vertices of the set of vertices.

Graphics processing systems

A graphics processing unit having a shader execution unit for executing a plurality of shader routines in order to perform a predetermined sequence of shader operations. The shader operations include a tessellation operation which receives as inputs tessellation control data and an input list of input data for M input vertices, and generates at least output data for P output vertices. For each output vertex, the controller allocates a tessellation shader routine from the set of shader routines, and the shader execution unit is configured, each time the tessellation shader routine is executed for an associated output vertex: (i) to compute, in dependence on the tessellation control data and the associated output vertex, tessellation coordinate data; and (ii) to compute from the input data for the M input vertices, and the tessellation coordinate data generated in step (i), the output data for the associated output vertex.

Graphics processing unit and method for performing tessellation operations

An apparatus for processing primitives in a tile-based graphics processing system includes processing circuitry which is configured to determine, for a group of plural primitives, the rendering tiles that the group of primitives should be processed for. The processing circuitry is also configured to store, for the group of primitives, a data entry containing an indication of the identity of the plurality of primitives in the group of primitives, and an indication of the rendering tiles that it has been determined the group of primitives should be processed for.

Methods and apparatus for processing computer graphics primitives in tile-based graphics rendering system

A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tileof a frame bufferto form one or more new pixel values are stored within a tile memory. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

Forming a windowing display in a frame buffer

A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list. This enables the same graphics processing unit to be used for both binning and rasterization operations, significantly reducing the size of the graphics system, while also allowing improvements in performance and energy consumption.

Tile-based graphics system and method of operation of such a system

A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments. The fragment processors subsequently receive and compute a result for each fragment, which is combined using the combiner to produce the final pixel value.

Color computation of pixels using a plurality of vertex or fragment shader programs

A method and apparatus forward a hardware call from a driver to graphics hardware via a virtual connection. Specifically, the method and apparatus process graphical data in a system having the driver, which produces a hardware call for the controlling the operation of the graphics hardware. As noted above, the method and apparatus first establish the virtual connection between the driver and the graphics hardware. Next, the hardware call is forwarded to the graphics hardware via the virtual connection.

Distributed graphics processing apparatus and method

A system and method for distributing data (e.g., imaging data such as pixels, or 3D graphics data such as points, lines, or polygons) from a single or a small number of data sources to a plurality of graphical processing units (graphics processors) for processing and display is presented. The system and method provide a pipelined and multithreaded approach that prioritizes movement of the data through a high-speed multiprocessor system (or a high-speed system of networked computers), according to the system topology. Multiple threads running on multiple processors in shared memory move the data from a storage device (e.g., a disk array), through the high-speed multiprocessor system, to graphics processor memory for display and optional processing through fragment programming. The data can also be moved in the reverse direction, back through the high-speed multiprocessor system, for storage on the disk array.

Growing community of inventors

Mountain View, CA, United States of America

David R Shreiner