Motorola Corporation

Asm America, Inc.

Standard Microsystems Corporation

Gain Technology Corporation

David R Rodriguez

Dennis L Goodwin

Allan Doley

Kenneth O'Neill

Gerben Vrijburg

Ravinder K Aggarwal

Richard S Griffith

William Walsh

Patrick J Holly

David R Rice

Olivier J Lauvray

Gary M Segal

A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad&#x2014;within their respective pad circuits in the affected digital I/O pads&#x2014;may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

Pad ESD spreading technique

An apparatus and method for reducing particles in reactors. The apparatus includes an enclosure with a wafer handling chamber connected by an isolation gate valve to a processing chamber. Pipes deliver purge gas into the wafer handling chamber to eliminate particles from the enclosure. A pilot operated back pressure regulator regulates the delivery and removal of the purge gas. The apparatus actuates the isolation gate valve in a controlled rate to reduce disturbances from the purge gas entering into the enclosure. A Bernoulli wand is provided for lifting and holding a single semiconductor wafer. A dome loaded regulator actuated by a pilot gas is used to control the ramp rates of gas to the Bernoulli wand. The ramping rates of the Bernoulli wand gas can be controlled by restrictions and check valves in the pilot gas line. The apparatus also utilizes ionizers in the purge gas lines entering the wafer handling chamber and load locks. Through the use of an alpha particle emission source in the purge gas line prior to the load lock and wafer handling chamber, the purged gas molecules are ionized. The ionized gas is conductive and therefore discharges static so that wafers are no longer attracted to each other by electrostatic force. In addition, the apparatus includes means for reducing gas flow turbulence when switching valves within the reactor.

Substrate handling chamber

An integrated circuit ( ) includes a current mirror having high output impedance and also having an output device with a low drain-to-source saturation voltage.

Integrated circuit with improved current mirror impedance and method of operation

An apparatus and method for reducing particles in reactors. The apparatus includes an enclosure for processing the semiconductor wafers. The enclosure has a wafer handling chamber connected by an isolation gate valve to a processing chamber. Additionally, the apparatus includes pipes for delivering a purge gas into the wafer handling chamber. The purge gas is used to eliminates particles from the enclosure. The apparatus also includes a pilot operated back pressure regulator for regulating the delivery and removal of the purge gas from the enclosure. The apparatus actuates the isolation gate valve in a controlled rate to reduce disturbances from the purge gas entering into the enclosure. The apparatus also includes a Bernoulli wand for lifting and holding a single semiconductor wafer. A dome loaded regulator is used to control the ramp rates of the gas to the Bernoulli wand. The dome loaded regulator is actuated by a pilot gas. The ramp up and ramp down rates of the Bernoulli wand gas can be control by a multitude of restrictions and check valves in the pilot gas line. The apparatus also utilizes ionizers in the purge gas lines entering the wafer handling chamber and load locks. Through the use of an alpha particle emission source in the purge gas line prior to the load lock and wafer handling chamber, the purged gas molecules are ionized. The ionized gas is conductive and therefore discharges all static inside the semiconductor equipment. By removable of the static charge particle and wafers are no longer attracted to each other by electrostatic force. In addition, the apparatus includes means for reducing gas flow turbulence when switching valves within the reactor.

System and method for reducing particles in epitaxial reactors

A power cut detection and recovery system (36) provides for the recovery of an electronic apparatus (20) in response to a momentary interruption in the voltage level of a power supply (46) coupled to that apparatus. The system includes a level detecting circuit (80) coupled to the power supply (46) for monitoring the voltage supplied to the apparatus (20). The system further includes internal reference supply circuits (86) that provide voltage and current references to operate the apparatus (20). A power cut monitor and reference control circuit (84) is coupled to the level detecting circuit (80) and is capable of causing the internal reference supply circuits (86) to remain enabled upon the detection of a momentary cut in the externally supplied power (46). A second level detecting circuit (90), dependent on the internal reference supply circuits (86), and the power cut monitor and reference control circuit (84) are coupled to an under voltage monitor and recovery circuit (88) that can cause the apparatus (20) to restart upon the recovery of the voltage level to a value above a predetermined level. By maintaining the internal reference supply circuits (86) in an enabled state, the apparatus (20) is able to restart in its pre-interruption state if the voltage level remains above a POR level.

System and method for recovering from a power supply interruption

A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers (21, 24, 27) between the interconnect layers (23, 26, 29) wherein a portion (48) of the top interconnect layer (29) overlies portions (47, 42, 43) of the underlying interconnect layers (23, 26) and wherein a portion (47) of the middle interconnect layer (26) does not overlie the portions (42, 43) of the bottom interconnect layer (23) and also does not overlie portions (32, 33) of one of the doped regions (20).

Semiconductor component comprising an electrostatic-discharge protection

A method and apparatus is provided for combining a plurality of signals in a digital pipelined signal adder. The method includes the steps of receiving (100) an upstream primary signal in a combiner and error checking 101 the primary signal in the combiner. When the primary signal passes error checking the primary signal is selected (103) and when the primary signal fails error checking a redundant signal is selected (102). The method further includes adding (104) the selected signal and a local input of the plurality of signals within the combiner to produce a downstream primary signal.

Growing community of inventors

Chicago, IL, United States of America

David R Rodriguez