Micron Technology Incorporated

Cray Incorporated

Sandia Corporation

Silicon Graphics, Incorporated

Other

David R Resnick

Van L Snyder

Gerald A Schwoerer

Kelly J Marquardt

Alan M Grossmeier

Roger A Bethard

Michael L Steinberger

Michael Higgins

Anand Ganti

H Lee Ward

William T Moore, Jr

R Paul Dixon

Kenneth R Wallgren

Kenneth W Iobst

Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder. Operation logic can be configured to receive data and perform operations thereon in accordance with internal control signals. A command decoder can be configured to receive command packets having at least a memory command portion in which a memory command is provided and data configuration portion in which configuration information related to data associated with a command packet is provided. The command decoder is further configured to generate a command control signal based at least in part on the memory command and further configured to generate control signal based at least in part on the configuration information.

Memories and methods for performing vector atomic memory operations with mask control and variable data length and data unit size

Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. Network node group may include a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node. Other apparatus, systems, and methods are disclosed.

Memory network methods, apparatus, and systems

A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same

Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second semiconductor memory unit to recover the data. The error correction information has a value equal to at least the value of the data store in the first memory unit.

Error correction in multiple semiconductor memory units

Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof. In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Methods and devices for temperature sensing of a memory device

Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a source configured to communicate signals to a memory device. At least one memory cube may coupled to the source by a communications link having more than one communications path. The memory cube may include a memory device operably coupled to a routing switch that selectively communicates the signals between the source and the memory device.

Flexible and expandable memory architectures

Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.

Failure recovery memory devices and methods

Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.

Extended single-bit error correction and multiple-bit error detection

A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The protection system is used to prevent at least some of a plurality of processors in a system from accessing addresses designated by one of the processors as a protected memory address. Until the processor releases the protection, only the designating processor can access the memory device at the protected address. If the memory device contains a cache memory, the protection system can alternatively or additionally be used to protect cache memory addresses.

Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same

A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache system operates in a manner that can be transparent to a memory controller to which the memory device is connected. Alternatively, the memory controller can control the operation of the cache system.

Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same

Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.

Error correction and recovery in chained memory architectures

Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.

Growing community of inventors

Boise, ID, United States of America

David R Resnick