Lsi Corporation

Lsi Logic Corporation

Other

Intel Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

David R Noeldner

Jackson L Ellis

Michael Bratvold

Graeme M Weston-Lewis

Richard Martin Born

David Matthew Springberg

Paul H Smith

Michael Ryan Buehner

Adrian R Pearson

Ricky F Bitting

Jonathan M Hughes

Gamil A Cain

Thomas R Bowen

Teddy Gordon Greer

Wei Tjan Lim

Niels Juel Reimers

Emily Po-Kay Chung

A self-encrypting drive (SED) comprises an SED controller and a nonvolatile storage medium (NVSM) responsive to the SED controller. The SED controller enables the SED to perform operations comprising: (a) receiving an encrypted media encryption key (eMEK) for a client; (b) decrypting the eMEK into an unencrypted media encryption key (MEK); (c) receiving a write request from the client, wherein the write request includes data to be stored and a key tag value associated with the MEK; (d) using the key tag value to select the MEK for the write request; (e) using the MEK for the write request to encrypt the data from the client; and (f) storing the encrypted data in a region of the NVSM allocated to the client. Other embodiments are described and claimed.

Technology for fine-grain encryption and secure key injection on self-encrypting drives

Described embodiments provide for transferring data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with a generic direct memory access (GDMA). The transmit data path includes a transmit (TX) buffer and the receive data path includes a receive (RX) buffer. The GDMA is programmed with a total transfer count and a transfer mode. The GDMA processes the movable data based on the total transfer count and the transfer mode by converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries, which translates frames of the moveable data between the TX data path and the RX data path and synchronizes the movable data between the TX buffer and the RX buffer with the status entries.

Direct memory access for loopback transfers in a media controller architecture

Various embodiments of the present invention provide systems and methods for processing data. As one example, a circuit is disclosed that includes a pre-detector that detects an estimated pattern in a digital input signal, and a summation element that subtracts the estimated pattern from the digital input signal to yield a noise estimate. The circuit further includes a data dependent noise prediction filter that is adaptively tuned to detect a noise pattern, and that filters the noise estimate to provide a filtered noise estimate.

Adaptive pattern dependent noise prediction on a feed forward noise estimate

Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating contexts corresponding to the data transfer requests and a buffer for storing one or more context pointers, each pointer corresponding to a context and an action by a system module associated with the context. A context processor is configured to complete a context when the action by a media controller module associated with the context is complete, remove each pointer from the buffer associated with the completed context, and determine whether an interrupt corresponds to the completed context and removed pointer. If no interrupt corresponds to the completed context, the completed context is cleared. If an interrupt corresponds to the completed context, the interrupt is provided to a master processor and a completed context recycler for recycling the completed context pointer to the context generator.

Interrupt queuing in a media controller architecture

Various embodiments of the present invention provide systems and methods for phase identification in data processing systems. As one example, a circuit is disclosed that includes a bank of matched filters with two or more matched filters tuned to detect patterns corresponding to a timing pattern sampled using different phases of a sample clock. In particular, the bank of matched filters includes at least a first matched filter tuned to detect a first pattern corresponding to the timing pattern sampled using a first phase of a sample clock, and a second matched filter tuned to detect a second pattern corresponding to the timing pattern sampled using a second phase of the sample clock. The circuits further include a logic circuit operable to determine whether the sample clock is closer to the first phase or the second phase based on an output of the first matched filter and an output of the second matched filter.

Timing phase detection using a matched filter set

Various embodiments of the present invention provide systems and methods for reduced clock rate data processing. As an example, a circuit is disclosed that includes a matched filter bank that receives a series of symbols at a rate corresponding to a sample clock. The matched filter bank includes a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, and a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence. The circuit further includes a detector circuit that processes a series of symbol proxies including the first symbol proxy and the second symbol proxy at a rate corresponding to a reduced rate clock. The reduced rate clock is the sample clock divided by a factor.

Reduced frequency data processing using a matched filter set front end

Described embodiments provide an apparatus for calculating an N-point discrete Fourier transform of an input signal having multiple sample values. The apparatus includes at least one input configured to receive the sample values and a counter to count sample periods. Also included are at least two parallel multipliers to multiply each sample value, with each of the multipliers having a corresponding multiplication factor. There is at least one multiplexer to select one of the at least two parallel multipliers. An adder sums the scaled sample values and an accumulator accumulates the summed sample values. N is an integer and the at least two parallel multipliers are selectable based upon the value of N and the value of the sample period count.

Method and apparatus for calculating an N-point discrete fourier transform

Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer context are generated, each receive-data thread corresponding to a data transfer between a host device and the media controller. Buffer threads corresponding to data transfer contexts for each transfer context are generated, each buffer thread corresponding to a data transfer between the receive data path and a buffer subsystem. The receive-data and buffer threads are tracked for each transfer context. For each tracked transfer context, data from the receive datapath is iteratively transferred to the buffer subsystem for a previous data transfer context of the buffer thread while data from the host device is transferred to the receive datapath for a subsequent data transfer context of the receive-data thread.

Context processing for multiple active write commands in a media controller architecture

Apparatus for calculating an N-point discrete fourier transform

Described embodiments provide a method of allocating resources of a media controller for a data transfer. A data transfer request is received from at least one host device, and includes a host device ID and a data transfer request ID. The media controller generates a Tag ID of the data transfer request based on the host device ID and the data transfer request ID, and generates a starting memory address of a tag table based on the Tag ID of the data transfer request. A tag count value is read from the starting memory address of the tag table. If the tag count value reaches a threshold, an absence of a tag overlap is determined and the Tag ID of the data transfer request is added to the tag table at the starting memory address.

Command tag checking in a multi-initiator media controller architecture

Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.

Context execution in a media controller architecture

Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device.

Coalescing multiple contexts into a single data transfer in a media controller architecture

Data-processing systems and methods are disclosed, including an I/O interface for managing the transfer of data between a processor and at least one memory. A processor can be associated with the I/O interface, such that the processor generically assembles a first or prior frame from among a plurality of frames, transmits the first or prior frame from among the plurality of frames over the I/O interface and thereafter processes and assembles a subsequent or second frame from among the plurality of frames while the first frame is transmitting, thereby providing enhanced flexibility and speed for the assembly and transmission of the plurality of frames across the I/O interface. The methods and systems disclosed also permit processor (i.e., software control) flexibility in managing the overall order and priority of frame transmission and protocol management, while enhancing hardware performance with respect to the sending of frames and control sequences without requiring real time interaction from the processor.

Task queuing methods and systems for transmitting frame information over an I/O interface

Described embodiments provide a method for calibrating a continuous-time filter having at least one adjustable parameter. A square-wave signal is filtered by a continuous-time filter having a cutoff frequency less than fs. The filtered signal is quantized at the rate fs. An N-point Fourier transform is performed of the quantized signal into N real output values and N imaginary output values. At least one of the real output values are accumulated to form a real output signal and at least one of the imaginary output values are accumulated to form an imaginary output signal. The real and imaginary output signals are summed to form an output signal, which is then squared. The squared output signal is compared to a comparison value. At least one parameter of the continuous-time filter is adjusted based upon the comparison. The steps are repeated until the squared output signal is approximately the comparison value.

Method and system for tuning precision continuous-time filters

The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be send. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

Growing community of inventors

Fort Collins, CO, United States of America

David R Noeldner