Brooktree Corporation

Conexant Systems, Inc.

David R Meyer

Warner B Andrews, Jr

Bradford C Lincoln

Douglas M Brady

An edge device for an ATM system includes a fire wall protection which proactively limits the number of cells per connection provided to the devices connected to the edge device. The edge device may be connected to ethernets, LANs, frame relay networks, communication equipment, work stations, or various other computer and communication equipment. The edge device preferably includes a counter for each connection associated with the ATM system. The counter is decremented each time a memory location in the host memory is utilized and incremented whenever the memory location is relieved of storing the data cell. An SAR unit operates to proactively prevent congestion by limiting each connection to a particular number of storage elements.

Apparatus and method for providing fire wall protection for systems in communication with an a synchronous transfer mode system

A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues. The SAR determines if either status queue is full by comparing the address written by the SAR into such status queue with the address written by the host periodically to the SAR where the host is in the status queue. The host determines if either control queue is full by comparing the address written by the host into such control queue with the address written by the SAR periodically to the host where the SAR is in the control queue.

Asynchronous transfer mode system for, and method of, writing a cell

A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, a cell the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.

Controller for ATM segmentation and reassembly

A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions. When more than one (1) cell is scheduled at the same position, one (1) cell is transferred on a preset priority basis to the corresponding time slot. The other cells are delayed for transfer subsequently in idle time slots (i.e. no cell normally scheduled) in the same or other priorities. The cell delays for each source are accumulated to a maximum preset value. When the cell delays accumulated for a source exceed the normal time spacing between cells from that source, the source transfers a cell in an idle time slot prior to the normally scheduled time slot to compensate for such delay.

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Lakewood, CO, United States of America

David R Meyer