Cray Research, Inc.

David R Kiefer

Nicholas J Krajewski

William T Moore, Jr

David J Johnson

Kent T McDaniel

Carl D Breske

Bricky A Stephenson

Michael R Edwards

Anthony A Vacca

Mark S Birrittella

Vernon W Swanson

Jan A Wikstrom

Stephen B Smetana

The invention comprises a plurality of stacked planar processing circuit boards surrounded on at least one side by a plurality of memory boards located substantially perpendicular to the planar processing boards, the processing and memory boards connected by orthogonal interconnect modules. The orthogonal interconnect modules allow closely-spaced orthogonal connection of the processing boards to the memory boards. The memory boards are of a densely packed design having a plurality of removeable memory chip stacks located on the memory boards.

High density interconnect apparatus

Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.

Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL)

Growing community of inventors

Chippewa Falls, WI, United States of America

David R Kiefer