Texas Instruments Corporation

David R Kee

Dennis D Davis

Buford H Carter, Jr

Richard E Johnson

Jesse E Clark

John Walter Orcutt

Charles E Williams

Angus W Hightower

Steven P Laverde

Hai Tran

A semiconductor device, especially a Ball Grid Array or Chip Scale Package, comprising an integrated circuit chip having at least one input/output terminal; a body of encapsulation material molded around said chip, forming a generally flat surface including at least one dimple having a suitable size and shape to receive a solder ball or solder paste; and said dimple having an electrically conductive solderable surface connected to said terminal.

Integrated circuit device with depressions for receiving solder balls and method of fabrication

A semiconductor device comprising a thermally conductive foil including a chip mount portion having first and second surfaces; an integrated circuit chip attached to said first surface; a body of encapsulation material molded around said chip and said first surface such that it leaves said second surface exposed; and said second surface comprising means for forming thermal contact, thereby creating a path for dissipating thermal energy from said chip. Said means for thermal contact comprise a configuration of said second surface suitable for direct thermal attachment to a heat sink. Alternatively, said means for thermal contact comprise a configuration of said second surface suitable for thermal attachment including solder balls between the chip and the heat sink.

Thermally enhanced semiconductor ball grid array device and method of fabrication

The invention relates to a single piece leadframe that can be used in current semiconductor device production. The leadframe has a plurality of segments in a horizontal plane, a chip mount pad in a different horizontal plane, and another plurality of segments connecting said chip mount pad with said leadframe. The latter plurality of segments has a geometry designed so as to tolerate bending and stretching beyond the limit of simple elongation based upon the inherent material characteristics. The chip mount pad of said leadframe provides direct thermal contact to an external heat conductor or heat sink by being designed so as to extend through the encapsulating package. The exposed chip pad can also be used electrically as a ground connection.

Exposed leadframe for semiconductor packages and bend forming method of

A method of low temperature securing a wire to a bond pad in a microelectronic semiconductor device which includes providing a semiconductor die having a bond pad thereon and providing a wire to be secured to the bond pad. One of the bond pad and wire is rotated relative to the other and the pad is contacted with the wire while the bond pad and the wire are rotating relative to each other until the interface of the wire and the bond pad diffuse into each other sufficiently to provide a bond therebetween upon cooling to secure the wire to the bond pad. Preferably the die is stationary and the wire is rotated. The wire is then cut to a predetermined length. By this method, it is possible to weld together dissimilar metals as well as metals which were previously no available in the fabrication procedures being utilized such as, for example, wherein the wire and the bond pad are both copper, wherein the wire is copper and the bond pad is aluminum, or wherein the wire is copper and the bond pad is titanium tungsten.

Microelectronic wire bonding using friction welding process

The invention is a single piece deep downset exposed lead frame (10) that can be used in current production processes. A single lead frame (10) has a die mount pad (12) that is formed with a downset or cavity into which the semiconductor die (20) is mounted. Wings (14, 15, 17, 18) lock the die pad in the device package (21) and increase the length of potential moisture paths (34a). The downset die pad (12) provides direct thermal contact of the die mount pad (12) to an external heat sink, eliminating the need for a heat slug internal to the package. The exposed die pad (12) can also be used as an RF ground connection to an RF circuit ground plane.

Downset exposed die mount pad leadframe and package

The invention is to a header for a power semiconductor device and a method for making the header. A ground pin is mounted or formed on the header mounting base and a header ground lead is placed over the ground pin and fused to the pin by a laser beam.

Laser bond header

A semiconductor device is formed without using a leadframe. A semiconductor device is formed in one area of a semiconductor chip and a second area includes conductors to which lead wires are bonded. The lead wires are used for mounting the semiconductor device.

Leads for semiconductor chip assembly and method

A lead from 10 carries an integrated circuit on a die support pad 14. The lead frame has a dam bar including a transverse portion that extends between adjacent leads (20) for limiting mold flash. The dam bar transverse portion 26 is entirely severed from the adjacent leads for final removal by a metal punch 33 along with the supporting web 16.

Growing community of inventors

Richardson, TX, United States of America

David R Kee