Intel Corporation

David R Jackson

Ali S Oztaskin

Leonard W Cross

Stephen W Kiss

Miles F Schwartz

Lily Pao Looi

Suresh S Chittor

Robert A Jacobs

Rajee S Ram

Peter B Bloch

Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.

System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order

A device and method for servicing data requests from a processor or other input/output interface in a multi-processor environment by accessing a full or partial cache line of data. A system data chip is used to access the cache line of data using a bit pattern supplied by a system address chip. This access and transmission of data to the processor or the input/output interface is controlled by a control/status unit in the system data chip based on the value of control valid signals which include a first valid (DxV) signal and a second valid (CxV) signal. Also, data may be stored and retrieved in a first data format (linear chunk order) or a second data format (critical chunk order). When control by the control/status unit is based on the DxV signal value, a read of a data chunk may occur immediately after a write to temporary storage if the data is in the same chunk order and a merge or combination operation is not taking place. When control by the control/status unit is based on the CxV signal, the entire cache line of data must be written to temporary storage prior to the reading of any data. In this way read operation are optimized to minimize latency and maximize throughput.

Device and method to minimize data latency and maximize data throughput using multiple data valid signals

A method and apparatus for third party agent transaction deferral on a host bus. A host bus transaction request is received from a device, and transaction information related to the transaction request is stored in an out of order queue. An indication is received from the third party agent that the transaction has been deferred, and the stored transaction information is updated to reflect that the transaction has been deferred.

Method and apparatus for deferring transactions on a host bus having a third party agent

An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.

Method and apparatus for supporting power conservation operation modes

Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

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Hillsboro, OR, United States of America

David R Jackson