International Business Machines Corporation

Other

Infineon Technologies North America Corp.

Siemens Aktiengesellschaft

Infineon Technologies Ag

David R Hanson

Gerhard Mueller

Toshiaki Kirihata

Hoki Kim

Gregory J Fredeman

John W Golz

Dureseti Chidambarrao

David M Onsongo

Kangguo Cheng

Huilong Zhu

Carl John Radens

Louis L Hsu

Rajiv V Joshi

Ping-Chuan Wang

Chengwen Pei

Kai D Feng

Louis Lu-Chen Hsu

Johnathan E Faltermeier

Hon-Sum Philip Wong

Paul Christian Parries

Gerd Frankowsky

Xinlin Wang

Brian L Ji

Gunther Lehmann

Kris V Srikrishnan

Wolfgang Hokenmaier

Joseph Natonio

James D Rockrohr

Edward R Pillai

David Bisson

Hance H Huston, Iii

An on-chip frequency calibration apparatus is described. A ring oscillator generates a clock signal. A trimmable resistor is coupled to the ring oscillator. A frequency detector detects the frequency of the clock signal generated from the ring oscillator. The frequency detector includes a frequency divider component that divides the frequency of the clock signal by a predetermined number to derive an output signal having a pulse duration that is equal to at least one period of the clock signal, a capacitor, a capacitor charging current source, and a capacitor charge transistor directs a charging current generated from the capacitor charging current source to the capacitor as a function of the output signal generated from the frequency divider component. A resistor trimming unit trims the trimmable resistor in response to determining that the frequency detected by the frequency detector is less than a target frequency threshold.

Frequency calibration with real-time resistor trimming

An FET including a gate conductor overlying a channel has first and second threshold voltages, respectively of a first and a second magnitude. When the second magnitude exceeds the first magnitude, both threshold voltages become effective concurrently. The FET operates responsive to a gate-source voltage between the gate conductor and source in states that include a non-conductive state. When the magnitude of the gate-source voltage is lower than the first and second magnitudes, the source-drain current is negligible. The first conductive state when the magnitude of the gate-source voltage exceeds the first magnitude and is lower than the second magnitude, the source-drain current operates at ten or more times exceeding the negligible value. When the second conductive state exceeds the magnitude of the gate-source voltage and exceeds the first and second magnitude, the state the source-drain current has a second operating value ten or more times higher than the first.

Field effect transistor having multiple conduction states

A universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.

Monitoring system for detecting and characterizing classes of leakage in CMOS devices

An illuminated identification system comprises a light chamber, a lighting means, an opaque identification stencil, a flashing means, a power on/off switch for the lighting means, and an on/off switch for the flashing means. The light chamber is environmentally sealed, and has one surface which is non-opaque. The lighting means is in series with a power source, and is located in the light chamber. The opaque identification stencil is placed over the non-opaque light chamber surface. When the power switch and the flashing means are both on, the flashing means causes the lighting means to flash on and off. Further, the power switch, and/or the on/off switch for the flashing means, may be operated by remote control.

Illuminated identification system

A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor ('multi-state FET') having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or 'low' conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.

Programming and determining state of electrical fuse using field effect transistor having multiple conduction states

A random access memory (RAM), such as a dynamic RAM (DRAM) or embedded DRAM (eDRAM) on a CMOS integrated circuit (IC) logic chip. Memory banks drive one line of a connected global data line pair to develop a difference signal on the pair. Simultaneously, a global signal monitor line discharges to develop a signal that mirrors the signal developing on one of the pair. When the global signal monitor line discharges sufficiently to indicate that the difference signal is large enough to sense, a global sense control sets a global data sense amplifier, the memory banks drive shuts off, and the global sense control initiates restoring global data line.

DRAM with self-resetting data path for reduced power consumption

An integrated circuit is provided which includes a sensing circuit. In the sensing circuit, a pair of conductors including a first conductor and a second conductor are adapted to conduct a first differential signal having a small voltage difference and a second differential signal having a rail-to-rail voltage difference. A sense amplifier is coupled to the pair of conductors, the sense amplifier being operable to amplify the first differential signal into the second differential signal. The sensing circuit further includes a multiple conduction state field effect transistor or 'multi-state FET' which has a source, a drain, and a gate operable to control conduction between the source and the drain. The multi-state FET has a first threshold voltage and a second threshold voltage which is effective at the same time as the first threshold voltage such that the multi-state FET is operable by the gate voltage to switch between an essentially nonconductive state, a first conductive state when a gate-source voltage applied between a gate and a source of the FET is between the first threshold voltage and the second threshold voltage, and a second conductive state when the gate voltage exceeds the second threshold voltage. The multi-state FET is used to perform an operation included in amplifying the first signal into the second signal by the sense amplifier.

Sense amplifier including multiple conduction state field effect transistor

A circuit and method of controlling integrated circuit power consumption using phase change switches where the phase change switches switchably couple and decouple power sources to logic blocks in response to a programming voltage.

Circuit and method of controlling integrated circuit power consumption using phase change switches

A microelectronic element is provided having a major surface, the microelectronic element including a first capacitor formed on a sidewall of a first trench, the first trench being elongated in a downwardly extending direction from the major surface. The microelectronic element further includes a second capacitor formed on a sidewall of a second trench, the second trench being elongated in a downwardly extending direction from the major surface, wherein a top of the first capacitor is disposed at a first depth from the major surface, and a top of the second capacitor is disposed at a second depth from the major surface.

Microelectronic element having trench capacitors with different capacitance values

A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Low power manager for standby operation of a memory system

In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

Dynamic random access memory with smart refresh scheduler

As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.

Bi-directional read write data structure and method for memory

A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.

Data path calibration and testing mode using a data bus for semiconductor memories

An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

Structure and method of making three finger folded field effect transistors having shared junctions

A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

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Brewster, NY, United States of America

David R Hanson