Lewis Rhodes Labs, Inc.

Emulex Design & Manufacturing Corporation

National Technology & Engineering Solutions of Sandia, LLC

Giganet, Inc.

David R Follett

Maria Clara Gutierrez

James B Williams

Nitin Dhiroobhai Godiwala

Shawn Adam Clayton

Pamela L Follett

Richard F Prohaska

James Bradley Aimone

David S Wells

Harold E Roman

John H Naegle

Craig Michael Vineyard

Frances S Chance

Jonathon W Donaldson

Shawn A Clayton

Various technologies pertaining to allocating computing resources of a neuromorphic computing system are described herein. Subgraphs of a neural algorithm graph to be executed by the neuromorphic computing system are identified. The subgraphs are each executed by a group of neuron circuits serially. Output data generated by execution of the subgraphs are provided to the same or a second group of neuron circuits at a same time or with associated timing data indicative of a time at which the output data was generated. The same or second group of neuron circuits performs one or more processing operations based upon the output data.

Neuromorphic computing architecture with dynamically accessible contexts

A method for processing data is provided. Data is identified by a computer system. The data is processed in parallel by the computer system using temporal transformations to form pieces of temporal data. The pieces of temporal data are placed by the computer system in an order as the pieces of temporal data are generated by the temporal transformations to form a sequence of temporal data. The order of the sequence is based on a priority of when the pieces of temporal data should be processed, enabling performing an action.

Temporal data system

A data stream processing unit (DPU) and methods for its use and programming are disclosed. A DPU includes a number of processing elements (PEs) arranged in a physical sequence. Each datum in the data stream visits each PE in sequence. Each PE has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. Each computing circuit implements a finite state machine that operates on the data and metadata inputs as a function of its position in the sequence and a data context, producing an altered partial computational state that accompanies the datum. When the data context changes, the current state of the finite state machine is stored, and a new state is loaded. The processing elements may be collectively programmed to perform any desired computation.

Context switching for computing architecture operating on sequential data

A data stream processing unit (DPU) and method for use are provided. A DPU includes a number of processing elements arranged in a sequence, and each datum in the data stream visits each processing element in sequence. Each processing element has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. The computing circuit for each processing element operates on the data and metadata inputs as a function of its position in the sequence, producing an altered partial computational state that accompanies the datum. Each computing circuit may be modeled, for example, as a finite state machine, and the collection of processing elements cooperate to perform the computation. The computing circuits may be collectively programmed to perform any desired computation.

Computing architecture for operating on sequential data

A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

System and method for scheduling message transmission and processing in a digital data network

System and method for regulating message flow in a digital data network

A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.

A computer interface system for communicating between computers along designated circuits is provided. An interface unit is provided in each host computer. Each unit includes a memory map that stores a map of physical addresses that correspond to virtual addresses for each application involved in a communication link. Each transfer of data is designated by a circuit that is established using the ATM protocol. The circuit is recognized by each unit involved in the communication and facilitates direct access of each host computer's main memory with minimum intervention from the operating system. A novel dynamic buffer management system is also provided.

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Boxborough, MA, United States of America

David R Follett