Texas Instruments Corporation

David R Cotton

Joe R Trogolo

Roy Clifton Jones, Iii

Dan M Mosher

Larry Latham

Cornelia H Blanton

Taylor R Efland

James Robert Todd

Dale J Skelton

Bob Todd

Andrew Marshall

Wayne T Chen

William Robert Krenik

Baoson Nguyen

Kenneth G Buss

Shaibal Barua

Edward N Jeffrey

Dennis V Hahn

John K Lee

A charge pump uses switching transistors including a PMOS transistor (P,), a first transistor (N,), and a second transistor (N,) instead of diodes (D,, D,) to control the transfer of charge from a pump capacitor (,) to a storage capacitor (,). The voltage (,) at the storage capacitor (,) is applied to a level shifter (,) and to the source of the PMOS transistor (P,) which, in turn, biases the first transistor (N,) during low state of an oscillating waveform (,B). A supply rail (,) charges the pump capacitor (,) when the first transistor (N,) is in its active region during the low state of the oscillating waveform (,B) and turns OFF during the high state of the waveform (,B) causing the charge on the pump capacitor (,) to be transferred to the storage capacitor (,). The level shifter (,) is used to synchronize the oscillating waveform (,B) so that no charge is lost from the pump capacitor (,) back to the supply and minimal charge is conducted through a parasitic diode (,).

Device for improving the switching efficiency of an integrated circuit charge pump

A system for driving hard disk drive spindle and actuator motors is disclosed. The system comprises a spindle motor control circuit (120), a spindle motor power circuit (210), an actuator motor control circuit (110), and an actuator motor power circuit (210). The spindle motor control circuit (120) and the actuator motor control circuit (110) are formed on a first substrate (100). The spindle motor power circuit (210) and the actuator motor power circuit (220) are formed on a second substrate (200). The system also includes at least one disk (22) attached to a rotatable spindle (21), a spindle motor (400) for receiving and being energized by the spindle motor power signals, and for controlling the rotation of the spindle (21), a plurality of disk read heads (12) adjacent to the disks (22), and an actuator motor (300) for receiving and being energized by the actuator motor power signals, and for controlling the position of the disk read heads (12).

Method and circuit for driving hard disk drive spindle and actuator

An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.

Multiple transistor integrated circuit with thick copper interconnect

Method of making a multiple transistor integrated circuit with thick

A high current power transistor is provided that comprises a drain region that includes a highly-doped drain region (54) and a lightly-doped drain region (50). The channel region (52) is activated by a gate conductor (32). The channel region separates the lightly-doped drain region (50) from a D-well region (40). A sidewall insulator body (44) is used to form the lightly-doped drain region (50) and the lightly-doped drain region (54). The transistor is formed in an active region (20) which comprises a portion of an n-type epitaxial layer (12) formed outwardly from a p-type substrate (10). The isolation structures (14) and (16) as well as the epitaxial layer (12) provides for a transistor that can be used in both source follower and common source configurations.

Isolated power transistor

Circuitry (46, or 28 and 70) for thermally separating a power integrated circuit device (12) from a plurality of other such devices (14, 16, and 18) on a common power integrated circuit chip (10) operate when the device (12) reaches a thermal shutdown temperature setpoint (56) with an output current at a predetermined current limit (54). The circuitry 46, or 28 and 70 switches the output current to a shutdown current level (57) until the device (12) reaches a predetermined lower temperature setpoint (58). Circuitry (46, or 28 and 70) restores the output current level to the predetermined current limit only after the device (12) reaches both the predetermined lower temperature setpoint (58) and a predetermined circuit setpoint (62 or 74). The circuit setpoint (62 or 74) associates with the temperature of the device (12) and may be either a yet lower temperature setpoint (62) or a specified time delay (74). The above steps are repeated to lower the average temperature of the device (12) and thereby thermally separate the device (12) from the other of such devices (14, 16 and 18) on the common power integrated circuit chip (10).

Method and apparatus for thermally separating devices on a power

The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications. The bipolar power transistors are more rugged and have higher power handling capabilities than DMOS devices. Thus the bipolar transistors can be used for any out-stage configuration, including low side, high side, half bridge and full bridge output circuits. The versatility of the present process flow allows the fabrication of MOSFET, BiMOS, BiCMOS, and bipolar technology either discretely or with high power or low power NPN or PNP devices.

Method of forming complementary bipolar and MOS transistor having power

An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

Complementary bipolar and MOS transistor having power and logic

An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.

Integrated circuit that combines multi-epitaxial power transistors with

Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).

Integrated power DMOS circuit with protection diode

A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Growing community of inventors

Plano, TX, United States of America

David R Cotton