Freescale Semiconductor,inc.

Motorola Corporation

International Business Machines Corporation

Nxp Usa, Inc.

David R Bearden

Ravindraraj Ramaraju

Prashant U Kenkare

Andrew Christopher Russell

Troy L Cooper

Shayan Zhang

James David Burnett

Hector Adrian Sanchez

Kenneth R Burch

Charles Eric Seaberg

Firas Najeh Abughazaleh

Raymond L Vargas

Mark David Bolliger

William C Moyer

David Theodore Blaauw

Michael D Snyder

Bradford Lawrence Hunter

Klas Magnus Bruce

James Andrew Welker

Gordon J Robbins

Bradley J Garni

Huy Nguyen

Salim Chowdhury

Jogendra C Sarker

Elie I Haddad

Ambica Ashok

Aurobindo Dasgupta

Ravi Gupta

Venkataram Mooraka

Arthur R Piejko

Cody B Croxton

Sunitha Manickavasakam

Venkatarama Mohanareddy Mooraka

George P Hockstra

Pradipto Mukherjee

An apparatus is disclosed that includes a phase detector circuit for generating a first pulse signal based on first and second input clock signals. A first circuit adjusts the first pulse signal by delaying transmission of a leading edge of the first pulse signal, but not a trailing edge of the first pulse signal. A charge pump circuit charges or discharges a capacitor based on the adjusted first pulse signal, and a voltage controlled oscillator (VCO) circuit generates an output clock signal with a frequency that depends on a voltage on the capacitor.

Fractional N PLL with sigma-delta noise cancellation

A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value. A second counter includes an input coupled to an output of another one of the N signal delay elements or the logic gate, wherein the second counter is configured to generate a second digital counter value. The PDC generates the digital output signal based on the low order bits and one of the first and second digital counter values.

Phase to digital converter

A temperature sensor circuit implemented in electronic circuitry that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensor circuit converts a voltage signal that is proportional to the temperature to a first digital value. The temperature sensor circuit converts a voltage signal that is inversely proportional to the temperature to a second digital value. The sensed temperature is determined as a function of a difference between the first and second digital values.

Temperature sensor circuit

Temperature sensing circuitry implemented on a semiconductor integrated circuit that senses the temperature at a site, digitizes the sensed temperature, and then outputs a signal representing such a sensed temperature. The temperature sensing circuitry converts a voltage signal that is proportional to the temperature to a frequency-based signal, which is converted to a digital bit value. A scalar factor is applied to another voltage signal that is inversely proportional to the temperature to produce a scaled voltage signal. The scaled voltage signal is converted to a second frequency-based signal, which is converted to a digital bit value, and then the two digital bit values are compared. The temperature is determined when the digital bit values substantially match.

Temperature sensor circuitry with scaled voltage signal

The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.

System and method for cache access

A method and data processing system for accessing an entry in a memory array by placing a tag memory unit () in parallel with an operand adder circuit () to enable tag lookup and generation of speculative way hit/miss information () directly from the operands () without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands () are applied with a carry-out value (Cout) to a content-addressable memory array () to generate two speculative hit/miss signals. A sum value (EA) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output ().

Memory management unit tag memory

A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.

System and method for memory array access with fast address decoder

An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.

Electronic circuit having shared leakage current reduction circuits

A multi-core system on a chip () is described in which a speed information for each core (), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g,) to run any applications or tasks that can not be executed on a plurality of cores.

Multi-core system on chip

A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.

Data processor having multiple low power modes

A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.

Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand

A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.

Soft error correction in a memory array and method thereof

A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Integrated circuit having low power mode voltage regulator

An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.

Memory device having shifting capability and method thereof

A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.

Growing community of inventors

Austin, TX, United States of America

David R Bearden