Lsi Logic Corporation

Teralogic, Inc.

Zoran Corporation

Csr Technology Inc.

Apple Inc.

David R Auld

Gerard K Yeh

Bruce Holmer

Greg Maturi

Peter Trajmar

Hong-Jyeh Jason Huang

Nishit Kumar

Darren Duane Neuman

Warangkana Tepmongkol

Joseph Cesana

C Dardy Chang

Meng-Day Yu

Anil Khubchandani

Hsiang O-Yang

Chen Chen

Lei He

Kwok K Chau

Larry Forsblad

Anoush Khazeni

Zeljko Markovic

Raymond H Lim

Timothy J Vogt

Roy J Askeland

Gerard Kuang-Chang Yeh

Xianliang Zha

Hank Guo

Edward Wang

Steve Chiou

Kevin P Acken

Jackson F Lee

According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

Interactive set-top box having a unified memory architecture

The invention provides techniques to implement unique identifier for an integrated chip and how this ID can be employed to enhance the security of content in personal video recorder type systems. The storage device can be a hard disk, a removable storage medium or any other type of storage medium. An integrated circuit (IC) within the personal video recorder stores a unique identifier that is used in for encryption and decryption of data stored on the storage device. Several embodiments are disclosed herein that maintain the secrecy of the unique ID such that it is not easily accessible thereby defeating the security scheme.

Unique identifier per chip for digital audio/video data encryption/decryption in personal video recorders

A television display system including a display system controller, a transmitter, and an integrated timing controller. The display system controller receives pixel data and pixel timing and control data, and responsive to a pixel data format corresponding to a selected communication standard of a plurality of communication standards that includes LVDS and at least one of RSDS and mini-LVDS, provides formatted pixel data formatted according to the pixel data format of the selected communication standard. The transmitter receives the formatted pixel data, and transmits the formatted pixel data for receipt according to a pixel data rate corresponding to the selected communication standard. The integrated timing controller receives the pixel timing and control data, and responsive to the selected communication standard being one of RSDS and mini-LVDS, generates pixel display timing and control signals to display the formatted pixel data at the pixel data rate corresponding to the selected communication standard on a television display.

System and method for integrated timing control for an LCD display panel

A receiver includes a sample rate converter configured to receive an input data stream having a variable data rate and to output a data stream having a fixed data rate. In some embodiments, the input data stream corresponds to digital video, digital audio and/or metadata, while in other embodiments the input data stream corresponds to any digital data stream that needs to be data rate converted for use by a receiving device. The sample rate converter is configured to track an externally sourced reference time signal corresponding to the input data stream.

Adaptive receiver

A sample rate converter includes a digital filter and control logic coupled to the digital filter. The digital filter is configured to receive an input data stream and to up convert the input data stream to produce an output data stream having a fixed data rate. The control logic configured to dynamically select a set of coefficients for taps in the digital filter during each clock cycle corresponding to the fixed data rate. The set of coefficients selected for each clock cycle is in accordance with a phase of the input data stream.

Adaptive sample rate converter

A method and a system for reconstructing a partial transport stream are described. One embodiment of the method includes time-stamping each packet when the packet arrives, storing of the selected subset of packets and the associated timestamps in a storage medium, reading the stored packets and their timestamps from the storage medium, and reconstructing the partial transport stream with the packets and their timestamps.

Reconstructing a partial transport stream

A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Method and apparatus for an integrated high definition television controller

The present invention is a method and apparatus for de-interlacing image data in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A de-interlacing circuit is coupled to the read interface circuit to de-interlace the image data in the patch from the buffer. A receive circuit is coupled to the de-interlacing circuit to re-organize the de-interlaced image data.

De-interlacing video images using patch-based processing

A method and apparatus for display of graphical data is described. The invention provides an architecture for graphics processing. The architecture includes pipelined processing and support for multi-regional graphics. In one embodiment, a graphics driver according to the invention can receive multiple independent streams of graphical data that can be in different graphical formats. The independent streams are synchronized and converted to a common format prior to being processed. In one embodiment, multi-regional graphics are supported with off-screen and on-screen memory regions for processing. The regions of the multi-regional graphic are rendered in an off-screen memory. The data in the off-screen memory are converted to a common format and copied to on-screen memory. The data in the on-screen memory is used to generate an output image. Alpha blending can also be programmed to provide multi-regional graphics or other graphical features. In one embodiment, graphics processing is programmable and can be paced using a set of registers.

Graphics engine architecture

The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.

Aspect ratio correction using digital filtering

The invention is a method and apparatus for processing image data stored in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A scale filter is coupled to the read interface circuit to scale the image data in the patch from the buffer. A receive circuit is coupled to the scale filter to re-organize the scaled image data.

Format conversion using patch-based filtering

Growing community of inventors

San Jose, CA, United States of America

David R Auld