Texas Instruments Corporation

David Quintin Bell

Abhijeet Ashok Chachad

Raguram Damodaran

Timothy David Anderson

Pierre Bertrand

Brian Cruickshank

Charles Lance Fuoco

Chunhua Hu

Peter Richard Dent

Samuel Paul Visalli

Dheera Balasubramanian

Akila Subramaniam

Roger Kyle Castille

Ran Katzur

Filip Moerman

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

Managing bandwidth allocation in a processing node using distributed arbitration

A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.

Method and system of debugging multicore bus transaction problems

A method of determining an adaptive early skip indication (ESI) threshold during block motion compensation encoding of digital video data is disclosed. The method includes setting an ESI threshold minimum value below which no degradation in the block motion compensation encoding occurs; setting an ESI threshold maximum value above which degradation in the block motion compensation encoding is considered unacceptable; determining that a processor load state of the processor during block motion compensation encoding is one of an overloaded state, a normal loaded state, and an under loaded state; when the processor load state is determined to be in an overloaded state, increasing the adaptive ESI threshold to a value below the ESI threshold maximum value thereby decreasing a number of macroblocks in the digital video data that are block motion compensation encoded; when the processor load state is determined to be in a normal loaded state, maintaining the adaptive ESI threshold at its current value; and when the processor load state is determined to be in an under loaded state, decreasing the adaptive ESI threshold to a value above the ESI threshold minimum value thereby increasing a number of macroblocks in the digital video data that are block motion compensation encoded. A block motion compensation encoding devices is also disclosed that implements the method above. A computer readable medium is also disclosed that stores instructions, which when executed by a processing unit, performs the method above.

Adaptive real-time video prediction mode method and computer-readable medium and processor for storage and execution thereof

A method includes generating a transfer configuration descriptor ('TCD'), the TCD includes information pertaining to data to be transferred. The method further includes dynamically configuring a direct memory access ('DMA) channel based on the TCD without using a CPU and transferring a group of data blocks by way of the DMA channel.

Interface and interrupt circuitry coupling data to host DMA circuitry

A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Memory error detection reporting

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Frederick, MD, United States of America

David Quintin Bell