Super Talent Electronics, Inc.

David Q Chow

Charles Chung Lee

Ming-Shiang Shen

Abraham C Ma

Frank I-Kang Yu

Frank Yu

Jim Chin-Nan Ni

I-Kang Yu

Abraham Chih-Kang Ma

Jianjun Luo

Chris Tsu

Siew Sin Hiew

Horng-Yee Chou

Edward W Lee

David Nguyen

Nan Nan

Tzu-Yih Chu

Sidney Young

A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices

An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket.

Backward compatible extended USB plug and receptacle with dual personality

According to certain embodiments of the invention, a flash memory card is manufactured using COB processes on a PCB panel with multiple micro cards PCB substrates. These micro memory cards are laid out in an array of 3&#xd7;5 matrixes of micro cards PCB substrates. A method of molding over a PCBA is utilized, contrary to a conventional method of having two or more pieces of package components to tape together. This results in a simpler structure without the notch which enables easier singulation process and the package is moisture resistance. The final product is a single piece versus two or three pieces glued up pieces and would not separate from pieces. The final product has high water and moisture resistance, low cost and fast manufacturing throughput, no seam and aesthetically more appeasing, can stack more layers of flash memory die, and be maximized XY spaces to accommodate larger size flash memory die.

High throughput manufacturing method for micro flash memory cards

A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels

A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.

Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear

Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.

Hybrid SSD using a combination of SLC and MLC flash memory arrays

An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

Extended USB plug, USB PCBA, and USB flash drive with dual-personality

High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

High endurance non-volatile memory devices

A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips

Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage.

Peripheral devices using phase-change memory

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

Synchronous page-mode phase-change memory with ECC and RAM cache

A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence ofetc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

Flash module with plane-interleaved sequential writes to restricted-write flash chips

A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.

Growing community of inventors

San Jose, CA, United States of America

David Q Chow