Thinking Machines Corporation

Network Engines, Inc.

Network Engineers, Inc.

David Potter

Robert A Wiley

Jerry Jarvis

W Daniel Hillis

Marshall Alan Isman

David C Douglas

Charles E Leiserson

Robert C Zak, Jr

Shaw-Wen Yang

Thomas J Moser

Christopher S Bonni

Joanne Sheehan

James Harvey Smith

David A Sheppard

David Stefanovic

Lawrence Genovesi

Bradley C Kuzmaul

John M Baron

Laurence N Provost

Thomas Savage

Eric D Sharakan

The invention herein pertains to improved methods and apparatus for electrically coupling components within a digital data system without the use of ribbon cables and other wires. The disclosed coupling device comprises a body member and at least one finger member. The body member physically and electrically couples with components mounted on a circuit board by mating with component pins extending on a solder side of the circuit board. The finger member is conjoined with the body member, and is a flexible, twistable, thin member containing electrically conductive vias coupled which couple the mounted components with an electrical connected located at the distal end of the finger member. The electrical connector at the distal end of the finger member can be a solder pad, a further member body, or other electrically coupling connector device. The finger member is designed to impact cooling air flow less than the disturbances created by conventional component coupling methods and apparatus, e.g., ribbon cable and wires, thereby increasing the effective heat dissipation within the digital data system.

Signal conducting applique and method for use with printed circuit board

A riser card, such as a peripheral component interconnect (PCI) card, attaches to a circuit board such as a mother board in a transverse orientation and has a first connector and a second connector attached to opposing sides of the card for receiving expansion cards. In one embodiment, the first connector is offset from the second connector with respect to an axis in the plane of the riser card. In another embodiment, the first and second connectors each have a first and last pin, and the first pin of the first card is opposite the first pin of the second connector. The riser card may mount one expansion board right side up, and the second board upside down. The first and second connectors can be female connectors which are each matable with a male connector on the corresponding expansion board, or can be card edge connectors. The expansion boards, when mated with the connectors, are substantially parallel to, but offset from the circuit board. Advantageously, the expansion boards consume less space in the housing by sharing a single riser card, and overall bus length may be substantially reduced between components in addition to providing additional, more open, or better channel space for cooling air flow. A preferred embodiment mounts centrally on a mother board, and provides two side channels for air flow cooling through the chassis of a rack-mounted web server data processor device.

Circuit board riser

A low profile, high density storage array includes a digital data storage unit, such as a rack-mount chassis, and a plurality of digital data storage devices such as disk drives, disposed within the array. The drives are spaced apart from a floor of the array on which they are mounted, e.g., via supporting &ldquo;sleds.&rdquo; In addition to facilitating insertion and removal of the drives from the array, air flow through or beneath these sleds cool the drives. The drives can be removably attached to the array via cam-like levers that facilitate mounting and dismounting of the drives from the chassis and its electrical circuitry.

Low profile, high density storage array

A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path through the interconnection network from the source processor to one or more of the processors which are to receive the message as destination processors. The interconnection network establishes, in response to a message from the source processor, a path in accordance with the address from the source processor in a downstream direction to the destination processors thereby to facilitate transfer of the message to the destination processors. Each destination processor generates response indicia in response to a message. The interconnection network receives the response indicia from the destination processor(s) and generates, in response, consolidated response indicia which it transfers in an upstream direction to the source processor.

Parallel computer system including arrangement for transferring messages

A data transfer arrangement for use in a data processing system comprising a processing array and at least one input/output unit and a host for issuing commands, including data transfer commands, to both the processing array and the input/output unit. The processing array and input/output unit include interfaces are interconnected by a bus and comprise an information transfer means, a control transfer means including a cycle identifier transfer means, and a transfer control means. The information transfer means transmits and receives information signals, including arbitration, target select and data signals, over information transfer lines of the bus. The cycle identifier transfer means transmits and receives cycle identifier signals over cycle identifier lines of the bus. The transfer control means is connected to the information transfer means and the control transfer means and enables a data transfer in a plurality of phases, including an arbitration phase, a selection phase and a data transfer phase. In particular, the control transfer means enables the information transfer means to transfer over the information transfer lines (i) arbitration signals in response to receipt of cycle identifier signals identifying an arbitration operation by the cycle identifier transfer means to thereby engage in an arbitration operation; (ii) target select signals during a target select phase in response to results of the arbitration operation to thereby engage in a target select operation, and (iii) data signals in response to results of the target select operation.

System for transferring blocks of data among diverse units having cycle

A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit or a replacement unit through an array of multiplexers.

Method and apparatus for operating multi-unit array of memories

Growing community of inventors

Acton, MA, United States of America

David Potter