Broadcom Corporation

Broadcom Europe Limited

Alphamosaic Limited

David Plowman

Stephen John Barlow

Timothy James Ramsdale

Robert Swann

Neil Bailey

Benjamin Sewell

Naushir Patuck

Ron Fridental

Graham John Veitch

Naushirwan Navroze Patuck

Gary Keall

Laurent Brisedoux

Clive Walker

Adrian Lees

Cressida Harding

Phil Elwell

Cresida Harding

Nel Bailey

Embodiments of imaging devices of the present disclosure automatically utilize simultaneous image captures in an image processing pipeline. In one embodiment, control processing circuitry initiates simultaneous capture of the first image by the first image sensor and the second image by the second image sensor; and image processing circuitry generates an enhanced monoscopic image comprising at least portions of the first image and the second image.

Dual image capture processing

Image data may be processed via one or more stages by a hardware image sensor pipeline (ISP) wherein one or more software processing steps may be inserted at any point within the hardware ISP. Output from any stage of the hardware ISP may be stored in memory. Stored hardware ISP output may be retrieved from memory and processed via one or more software processes. Results from the one or more software processes may be stored in memory and communicated to any stage of the hardware ISP for additional processing. In this regard, the hardware ISP and one or more processors may simultaneously process portions of image data. In addition, the hardware ISP and the one or more processors may be integrated within a chip.

Method and system for inserting software processing in a hardware image sensor pipeline

Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.

Method and system for processing image data on a per tile basis in an image sensor pipeline

A mobile multimedia device may be operable to crop a series of image samples received during an autofocus operation. Each of the cropped image samples may be scaled by the mobile multimedia device to fit a display unit in the mobile multimedia device. Each of the scaled image samples may then be displayed on the display unit for viewing during the autofocus operation. The received image samples may be cropped based on an operating mode in which the mobile multimedia device is currently operating. The autofocus operation may be initiated utilizing a shutter button in the mobile multimedia device. The autofocus operation may be terminated when a desired focus is achieved. After the autofocus operation is terminated, the mobile multimedia device may be operable to display one or more image samples received after the termination of the autofocus operation for continuous viewing, with or without further cropping and scaling.

Method and system for mitigating seesawing effect during autofocus

Embodiments of the present application automatically utilize parallel image captures in an image processing pipeline. In one embodiment, image processing circuitry concurrently receives first image data to be processed and second image data to be processed, wherein the second image data is processed to aid in enhancement of the first image data.

Concurrent image processing for generating an output image

A mobile multimedia device may be operable to initiate capture of a series of image samples of a scene, where the scene may comprise one or more objects that may be identifiable by the mobile multimedia device. An image for the scene may be determined by the mobile multimedia device utilizing the captured image samples based on motion associated with the identifiable objects. As soon as the image for the scene has been determined, the capture of the series of image samples may be terminated. The image may be determined when the amount of motion associated with the identifiable objects is below a particular threshold value. The identifiable objects may comprise one or more faces. The motion may be due to a gesture such as a wink or a smile received from one or more of the faces. The image may be determined when the gesture is detected.

Method and system for determining how to handle processing of an image based on motion

A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.

Register file with separate registers for compiler code and low level code

A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.

Vector processing system

A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction

A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

Narrow/wide cache

A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first group of cells all of which are located in the same column but in different rows.

Two dimensional data access in a processor

Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction

Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.

Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file

A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Growing community of inventors

Saffron Walden, United Kingdom

David Plowman