International Business Machines Corporation

David Peter Swart

Raymond Alan Richetta

Timothy Joseph Schmerbeck

Rick Allen Philpott

Robert Andrew Kertis

Donald Joseph Schulte

Christian J Goetschel

Randolph B Heineke

Robert A Greene

Richard Leo Galbraith

Delbert Raymond Cecchi

Gregory Scott Winn

Philip T Wu

Gerald Wayne Swift

David John Orser

Scott Allen Olson

Mark Andrew Bergquist

John Steven Mitby

Balsha R Stanisic

Hyung S Kim

A fiber optic transceiver array and a fiber optic transceiver channel are provided for short wave fiber optic communications. A fiber optic transceiver array for short wave fiber optic communications includes a series of fiber optic transceiver channels. Each fiber optic transceiver channel includes a plurality of test pads. A power distribution bypass capacitor is distributed along the series of fiber optic transceiver channels. A plurality of high voltage power supply and ground connections are coupled through the power distribution bypass capacitor and distributed around the series of fiber optic transceiver channels. A threaded high voltage power supply connection is provided to alternating ones of the series of fiber optic transceiver channels. A threaded ground connection is provided to alternating other ones of the series of fiber optic transceiver channels to reduce power noise generation and susceptibility to noise between adjacent channels. A power to ground decoupling capacitor included with each fiber optic transceiver channel also enhances power noise sensitivity reduction. A fiber optic transceiver channel for short wave fiber optic communications includes at least a high voltage power supply connection and a ground connection. A plurality of test pads includes at least a ground connection and a pair of differential output connections. A channel decoupling capacitor is positioned proximate to the pair of differential output connections.

Fiber optic transceiver array and fiber optic transceiver channel for short wave fiber optic communications

A fully balanced transimpedance amplifier for high speed and low voltage applications is provided. An input stage of the amplifier uses a matched pair of common source connected transistors with sources tied directly to ground to eliminate the Vds overhead usually found in differential pairs. The ground connection minimizes a source resistance noise component, while matching minimizes power supply noise generation and susceptibility for an array of amplifiers. Feedback resistors along with diode connected MESFETS determine the transimpedance of the amplifier. The nonlinearity of diodes helps to soften clipping. Transresistance also determined the noise generated by the amplifier, and the diode connected MESFETS offer lower noise than resistors for the same impedance. Stability is achieved through use of only a single stage of gain in a loop of the input stage, while additional gain is achieved through cascading in the input stage. A differential stage minimizes any difference in amplitude between two sides of the amplifier input stage. Two stages of source followers provide buffering to drive a relatively low impedance load at the output of the amplifier. Single integrated capacitor coupling, for high bandwidth, low noise, low voltage operation with an integrated detector is provided.

Fully balanced transimpedance amplifier for high speed and low voltage applications

A gallium arsenide (GaAs) bandgap circuit includes a plurality of stacked GaAs transistors being connected as Schottky diodes which, together with an amplifier, provide a constant reference voltage being independent of a power supply voltage of the circuit.

Bandgap voltage reference circuit without bipolar transistors

An improved method and apparatus are provided for dc offset trim adjustment of a variable gain amplifier. The VGA has predetermined overall gain endpoints. A minimum gain and a maximum gain are identified for the VGA in a preferred operational range. The identified minimum gain and the identified maximum gain for the VGA in the preferred operational range are spaced apart inwardly from the VGA predetermined overall gain endpoints. The minimum gain for the VGA in operation is set, then trim adjustment of the VGA is provided to minimize an output of the VGA. Then the maximum gain for the VGA in operation is set, then dc offset trim adjustment of the VGA is provided to minimize an output of the VGA.

Method and apparatus for trim adjustment of variable gain amplifier

An analog output buffer circuit having a low quiescent power dissipation and a high current-driving capability is disclosed. In accordance with a preferred embodiment of the present invention, the analog output buffer circuit includes a capacitor and three transistors. The first transistor is coupled between a power supply and an output. The gate of the first transistor is utilized for receiving input signals. The second transistor is coupled between the output and ground. The capacitor is coupled between a gate of the first transistor and a gate of the second transistor such that voltages at the gate of the first transistor are related to voltages at the gate of the second transistor via the capacitor. Finally, the third transistor is coupled between the gate of the second transistor and a current source. This configuration allows the analog output buffer circuit to have a high current-driving capability while maintaining a low power dissipation during the quiescent period.

Analog output buffer circuit

A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Method and apparatus for generating a clock signal from a continuous

An integrated biquadratic, continuous-time filter section includes a plurality of operational transconductance amplifiers (OTAs). Simutaneously changing a transconductance (GM) of each of the OTAs is provided by adjusting a differential voltage applied to a plurality of differential transistor pairs of each OTA. Each of the OTAs include a plurality of current sources and a common mode feedback circuit for controlling a common mode output voltage level. Changing the transconductance of the OTA is independent of the common mode voltage level control.

Operational transconductance amplifier with independent transconductance

A method and apparatus are provided for adaptive chip trim adjustment for an integrated circuit. A plurality of switching devices have an unswitched state and a switched state. The unswitched state corresponds to one binary value, and the switched state corresponds to another binary value. A first trim word is provided by sensing the switching devices. The switching devices are temporarily bypassed, and an override bit pattern is supplied to simulate any desired pattern of the switching device states. The override bit pattern is used for simulating a switched or unswitched state for each of the plurality of switching devices.

Method and apparatus for adaptive chip trim adjustment

A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines. The feedback circuitry uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry that discharges the voltage level of the feedback circuitry when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.

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Pine Island, MN, United States of America

David Peter Swart