International Business Machines Corporation

Other

David Peter Pagnani

David W Dranchak

Leonard T Olson

Patrick Robert Zippetelli

Robert Joseph Kelleher

Frank David Ferraiolo

Thomas Mario Cipolla

Timothy C Reiley

Harry R Bickford

Peter G Ledermann

Mark F Bregman

Ekkehard F Miersch

Peter R Tomaszewski

Thomas P Comino

Ronald S Charsky

Donald J Malling

Richard Gregory Bednar

Walter V Vilkelis

Edward D Shockley

John Gow, Iii

Uh-Po E Tsou

Alejandro R Badia

An electrical circuit tracing apparatus wherein uniquely identifiable electrical signals are injected into deenergized electrical circuits at a circuit breaker panel. Once the apparatus is electrically connected to multiple deenergized branch circuits, a user may connect a circuit analysis box to successive electrical outlets. The circuit analysis box contains a readout that indicates the circuit number (i.e., 1-n, where n is the number of branch circuits simultaneously testable by the apparatus to which the particular electrical outlet is connected). If a particular electrical outlet is accidentally connected to more than one branch circuit, all of the circuits to which the analyzer box is connected are identified.

Apparatus for identifying a circuit breaker feeding a remotely disposed electrical outlet and method of using the apparatus

Chip carrier topology including a plurality of bond lines radiating from a line of chip pads to at least one of zero or more finger lines and zero or more voltage lines is defined by first collecting topology parameters selected from the set including the number of rows of fingers; the spacing between rows of fingers; finger style, said finger style being one of arc-of-circle, constant-bond-length, and encompassing-rectangle; location of voltage rings; value of voltage rings; location of chip pads; voltage of chip pads; dimensions of output fingers; minimum finger pair spacing; maximum finger angle with respect to its bond line; minimum spacing of bond line terminations at voltage rings; and minimum spacing of bond line terminations with respect to and adjacent bond line which terminates at a finger. A plurality of possible topology solutions are generated, and a single possible topology solution selected for further processing. From the single possible solution, a topology solution is generated by placing a middle finger with respect to a middle chip pad, processing alternative chip pads to the right and left sequentially from the middle chip pad selectively to position ring intercepts, inner row fingers and outer row fingers. The topology solution thus generated is evaluated and if acceptable, the result is output to an output file; if not acceptable for failure to conform to all topology parameters, the topology parameters are adjusted and the topology solution generated anew.

System and method for generating wire bond fingers

An electronic package assembly for being electrically connected to a conducting member (e.g., a printed circuit board) wherein the assembly includes a pair of substrates. The first substrate includes opposing circuit patterns, those on one surface being of higher density and thus adapted for having high density electronic devices mounted thereon. This high density pattern is electrically coupled to the lesser density second pattern which is connected to conductors of a second substrate. These conductors are of the lesser density also, and extend through a dielectric member for being coupled to conductors (e.g., copper circuit pads) on the conducting member. These conductors are in contact with the dielectric member at only three locations before the dielectric is connected to the electronic package assembly and the conducting member. Ready separability of various parts of the assembly is thus assured.

Dual substrate package assembly having dielectric member engaging

An electronic package assembly for being electrically connected to a conducting member (e.g., a printed circuit board) wherein the assembly includes a pair of substrates. The first substrate includes opposing circuit patterns, those on one surface being of higher density and thus adapted for having high density electronic devices mounted thereon. This high density pattern is electrically coupled to the lesser density second pattern which is connected to contacts of a second substrate. These contacts are of the lesser density also, and extend through a dielectric member for being coupled to conductors (e.g., copper circuit pads) on the conducting member. Ready separability of various parts of the assembly is thus assured.

Dual substrate package assembly coupled to a conducting member

Disclosed is a Musical Instrument Digital Interface emulator for testing the THRU port echo of a Musical Instrument Digital Interface device. The emulator has input devices for taking bitstream data from the THRU and OUT ports of the Musical Instrument Digital Interface device, comparing the THRU port bitstream data to the OUT port bitstream data, and generating a result of the comparison. Also disclosed is a method of testing the THRU port echo of a Musical Instrument Digital Interface device by reading the THRU bitstream and OUT bitstream of the Musical Digital Interface Device, bitwise comparing the two bit streams; and reporting the results of the comparison to an output means.

Midi through port hardware emulator

A compact, wide range inductor capable of being trimmed to a desired frequency value, comprising at least two individually tunable inductive elements of different resolution, disposed upon an insulative support. The inductor is usually placed within a hybrid circuit and trimmed after component population.

Tunable inductor

Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

Multilevel integrated circuit packaging structures

The disclosure describes a technique whereby the electrical characteristics of an electrical circuit in a package may be adjusted to a predetermined value by changes in the dielectric structure between two levels of circuitry. This adjustment in the composite dielectric structure is accomplished by changes in the electrical properties of the composite dielectric material, one level being preset to a value and the other level being adjusted by alterations of predetermined amounts that depend upon the performance desired.

Composite dielectric structure for optimizing electrical performance in

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Endicott, NY, United States of America

David Peter Pagnani