Texas Instruments Corporation

David Peter Foley

Alexander Tessarolo

Saya Goud Langadi

Alan Davis

Rajasekhar Reddy Allu

Amritpal Singh Mundra

Venkatesh Natarajan

Manish Bhardwaj

Prasanth Viswanathan Pillai

Prohor Chowdhury

Santosh Kumar Athuru

Thiru Gnanasabapathy

Devin Allen Cottier

Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.

Identifying a source of a function call and inheriting access permission

Methods, apparatus, systems, and articles of manufacture are described corresponding to immutable configuration of memory devices. An example memory includes a memory bank including a first portion and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and a controller coupled to the memory bank, the controller configured to determine whether to prevent data from being written to the first portion based on the configuration information.

Methods and apparatus to facilitate immutable configuration of memory devices

In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

Securing registers across security zones

Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

Methods, apparatus, and articles of manufacture to determine memory access integrity based on feedback from memory

Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Systems, methods, and apparatus to detect address faults

A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.

Configurable oversampling for an analog-to-digital converter

An integrated circuit (IC) chip and method of booting the IC are disclosed. The method includes determining whether a boot pin configuration has been programmed and responsive to determining that the boot pin configuration has been programmed, performing a boot method indicated in a user-defined boot table. Responsive to determining that the boot pin configuration key has not been programmed, the method performs a boot method selected from a factory-defined boot table.

Scalable boot options for a processor/controller

Multiple secure environments are established within a system on a chip (SoC) by defining a first secure region within a non-volatile memory in the SoC with a first set of parameters written into a predefined parameter region of the non-volatile memory. A second secure region within the non-volatile memory may be defined at a later time by a second set of parameters written into another predefined parameter region of the non-volatile memory. A security module is initialized each time the SoC is powered on by transferring the first set of parameters and the second set of parameters from the parameter region to the security module in a manner that does not expose the first set of parameters or the second set of parameters to a program being executed by the processor. The multiple secure regions of the SoC are enforced by the security module according to the parameter data.

Microcontroller with secure feature for multiple party code development

A system and method for preventing unauthorized access to the software of a semiconductor device is provided. The semiconductor device of the present invention includes a memory buffer in the data path between the processor core of the device and the memory of the device. A password for providing full communication in the data path is stored in a defined location in the memory. Upon reading the memory location, the password is provided to a code security module. The password provided to the code security module is compared to a data string provided by the user. If the password and the data string match, the password data path is open for communication between the memory and the processor core. If the password and data string do not match, the password data path is closed to communication between the memory and the processor core.

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Sugar Land, TX, United States of America

David Peter Foley