Cirrus Logic Inc.

Wolfson Microelectronics Limited

David Paul Singleton

Andrew James Howlett

John Bruce Bowlerwell

John Paul Lesso

Colin Steele

Kapil Sharma

Catherine A Hearne

Aniruddha Satoskar

Anindya Bhattacharya

Morgan Timothy Prior

Gordon James Bates

John Anthony Breslin

Jonathan Timothy Wigner

Louis Frew

Qi Cai

Toru Ido

Christopher M Dougherty

Sharjeel Riaz

Johnny Klarenbeek

An integrated circuit (IC), comprising: a converter comprising: one or more core devices; and one or more output internal nodes, each internal node coupled to one of the one or more core devices; protection circuitry comprising: one or more isolation switches, each of the one or more isolation switches coupled between a respective one of the one or more internal output nodes and a respective output external pin of the IC, wherein the protection circuitry configured to: monitor a characteristic at each respective external output pin of the IC; and if the characteristic is outside an operating specification of the one or more core devices, open one or more of the one or more isolation switches to isolate one or more of the one or more core devices from the respective external pin of the IC.

Protection circuitry

The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.

Audio amplifier circuitry

Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

Class D amplifier circuitry

This application relates to computing circuitry () for analogue computing. A plurality of current generators () are each configured to generate a defined current (I, I, . . . I) based on a respective input data value (D, D, . . . D). A memory array (), having at least one set () of programmable-resistance memory cells (), is arranged to receive the defined currents from each of the current generators at a respective signal line (). Each set () of programmable-resistance memory cells () includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module () is coupled to each of the signal lines to generate a voltage at an output node () based on the sum of the voltages on each of the signal lines.

Computing circuitry

Class D amplifier circuitry comprising: modulator circuitry; and output stage circuitry, wherein the modulator circuitry is configured to: receive an input signal and first and second carrier signals, wherein the second carrier signal is offset in amplitude with respect to the first carrier signal; generate first and second modulated output signals, each of the first and second modulated output signals being based on the input signal and the first and second carrier signals; and generate a plurality of control signals for the output stage circuitry per signal period of the modulated output signals, wherein the plurality of control signals are based on the first and second modulated output signals, and wherein at least one of the plurality of control signals per signal period comprises a signal level transition.

This application relates to ADC circuitry. An ADC circuit () has first and second conversion paths () for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes () to receive and convert full scale first and second analogue input signals (Ain, Ain) to separate digital outputs (Dout, Dout). In the second mode, the first and second conversion paths are both connected to the first input node (), to convert the first analogue input signal (Ain) to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector () select the first digital signal or the second digital to be output as an output signal based on an indication of amplitude of the first analogue input signal.

ADC circuitry

This application relates to analog-to-digital converter (ADC) circuitry (). A time-encoding modulator (TEM) has a comparator () and a loop filter () configured to generate a pulse-width-modulated (PWM) signal (S) in response to an input signal (S) and a feedback signal (S). A controlled oscillator, such as a VCO () receives the PWM signal and generates an output oscillation signal (S) with a frequency that varies based on a drive signal at a drive node (), e.g. a drive node of a ring oscillator (). The controlled oscillator () comprises at least one control switch () controlled by a switch control signal (S) generated from the received PWM signal so as to control the drive strength of the drive signal applied to the drive node (). The feedback signal (S) for the TEM () is derived from the controlled oscillator () so as to include any timing error between the PWM signal and the switch control signal (S) applied to said control switch.

Modulators

This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator () receives an analogue input signal (S) at an input node () and outputs a corresponding time-encoded signal (S) at an output node (). A hysteretic comparator () has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement () arranged to apply filtering to the feedback path. The hysteretic comparator () compares the input signal (S) to the feedback signal (S) with hysteresis. This provides a pulse-width modulated output signal (S) where the duty cycle encodes the input signal (S).

This application relates to methods and apparatus for voltage regulation. Embodiments relate to signal processing circuit () having a first and second processing path with respective first and second inputs (INP and INN). The first and second processing paths have respective first and second virtual earth nodes (P andN) at the input to a differential integrator (). A differential feedback path is configured to apply a feedback signal to each of the first and second virtual earth nodes so as to minimize any voltage difference between them. A regulator () is operable to monitor a voltage at one of the virtual earth nodes (P) against a reference voltage (V) and to generate a regulation signal to maintain the voltage at said monitored one of the first and second virtual earth nodes to be equal to the reference voltage. The regulation signal is applied to both of the first and second virtual earth nodes.

Voltage regulation of virtual earth nodes of a differential signal processing circuit

A driver apparatus is provided for controlling a light source array comprising at least first and second light sources, the light source array used for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. The driver apparatus comprises a single integrated circuit comprising processing means for processing image data received from the detector, a switching array comprising at least first and second switches for switching the respective first and second light sources, and a current source for controlling the flow of current through the light sources. In this way the LED switching circuitry that controls an LED array is 15 placed on the same integrated circuit (i.e. monolithic circuit) as the analogue processing circuitry that processes the image data, with the current source controlling the flow of current through the LEDs in the LED array.

Driver apparatus and method

A light source is protected by selectively coupling a shunt path in parallel with the light source, such that current is diverted away from the light source and through the shunt path. A detection circuit detects the current flowing in the shunt path when the shunt path is connected in parallel with the light source. A comparator determines whether the current flowing in the shunt path exceeds a predetermined threshold and, if so, prevents or limits the flow of current when the shunt path is disconnected from being in parallel with the light source. In this way, a current detector is provided for monitoring the flow of current in a shunt path, the current detector being configured to disable or limit the flow of current through a light source when a predetermined threshold is reached. This aspect of the invention has the advantage of enabling the current flowing through a light source to be controlled by monitoring the current in the shunt path rather than the path having the light source, thus enabling the maximum current to be controlled without potentially damaging the light source.

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Edinburgh, United Kingdom

David Paul Singleton