International Rectifier Corporation

Infineon Technologies Americas Corp.

David Paul Jones

Andrew Neil Sawle

Martin Carroll

Ling Ma

Robert J Montgomery

Hugo R Burke

Martin Standing

Timothy Donald Henson

Susan Johns

Hugo R G Burke

Matthew P Elwin

Ian Glenville Wagstaffe

Niraj Ranjan

Dev Alok Girdhar

Robert P Haase

Philip Parsonage

Vijay Viswanathan

Richard Bullock

Daniel Marvin Kinzer

Mark Pavier

Steven Thomas Peake

Kyle A Spring

Igor Bol

Kapil Kelkar

Daniel Cutler

Danish Khatri

Rupert Burbidge

Amarjit Dhadda

Omar Hassen

Phillip Parsonage

A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

Method for forming a reliable solderable contact

Solderable contact and passivation for semiconductor dies

A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.

Power semiconductor device with a double metal contact and related method

Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

Method for fabricating a shallow and narrow trench FET and related structures

Power semiconductor device with a double metal contact

According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.

Semiconductor wafer with reduced thickness variation and method for fabricating same

One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Buck converter power package

Power semiconductor device including a double metal contact

According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

Trench MOSFET and method for fabricating same

Solderable top metalization and passivation for source mounted package

A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Autoclave capable chip-scale package

A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the solderable contact such that a gap extends between the contact and the passivation layer. The device also includes a barrier layer disposed on the top surface of the electrode, and along the underside of the solderable contact and across the gap. The barrier layer may also extend under the passivation layer and may cover the entire top surface of the electrode. The barrier layer may also extend along the sidewalls of the electrode. The barrier layer may include a titanium layer or a titanium layer and nickel layer. The barrier layer protects the electrode and underlying die from acidic fluxes found in lead-free solders.

Protective barrier layer for semiconductor device electrodes

A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.

Semiconductor device fabrication using spacers

A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.

Trench type MOSgated device with strained layer on trench sidewall

A process is described to enable the manufacture of a thinned (&#x3c;50 &#x3bc;m semiconductor die) which can employ the use of standard equipment for the manufacture of the wafer and the packaging of the die singulated from the wafer. A standard thickness wafer (350 &#x3bc;m) first has junctions formed in its upper surface, but the surface is not yet metallized and patterned. A rigid front plate is connected to the upper surface by a removable adhesive and the wafer is back ground to its final thickness, for example, less than 50 &#x3bc;m. A back metal and a thick conductive backing plate are then fixed to the back metal. The rigid front plate is then removed and the front surface of the wafer is metallized and patterned. Die singulated from the wafer carry the thick permanent conductive backing plate and may be conventionally packaged as prior art 350 &#x3bc;m die. The wafer can initially be partially diced.

Process of manufacture of ultra thin semiconductor wafers with bonded conductive hard carrier

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South Glamorgan, United Kingdom

David Paul Jones