Motorola Corporation

David Paul Gurney

Kevin Lynn Baum

James Robert Kelton

Stephen Leigh Kuffner

Michael Russel Mannette

An automatic frequency control loop structure utilizes a dual selection automatic frequency control unit which is coupled to a differential phase unit and a coherent phase unit to provide a frequency corrected received signal output for efficient tracking of frequency offset drift and a much lower probability of loss of automatic frequency control loop lock. Thus, a signal from a coherent carrier recovery process provides additional benefit by utilization in adjusting frequency offset tracking performance.

Apparatus and method for maximizing frequency offset tracking

An improved automatic frequency correction acquisition system utilizes an automatic frequency correction (AFC) loop (22) having an acquisition mode in which an estimate of the frequency offset of a received carrier signal is rapidly acquired and a tracking mode in which the automatic frequency correction loop more accurately follows changes of the frequency offset. The AFC is switchable in response to predetermined control signals between the acquisition mode and the tracking mode. A carrier to impairment ratio estimator (36) is coupled with the automatic frequency correction loop (22) for estimating the carrier to impairment ratio of the incoming carrier signal. An automatic frequency correction controller (30) is coupled with the automatic frequency correction loop (22) and with the carrier to impairment ratio estimator (30) and is responsive to the carrier to impairment ratio estimate being at or above a preselected threshold value for producing a tracking control signal (24) comprising one of the predetermined control signals. The automatic frequency correction loop (22) is responsive to the tracking control signal (24) for switching from the acquisition mode to the tracking mode.

Method and apparatus for automatic frequency correction acquisition

A digital phase detector 100 receives a limited input signal 108 and inputs it and a reference oscillation 112 into an EXCLUSIVE NOR gate 102. The output 110 of the EXCLUSIVE NOR gate 102 is input to a gated N-bit counter 104, which produces an N-bit representation of the magnitude of the phase 115 of the signal 108. A sign detector 105 determines the sign of the phase of the signal by sampling the resultant 110 and combines the magnitude of the phase 115 with the sign of the phase to produce a digital numeric representation of the phase of the signal 116.

Digital phase detector with integrated phase detection

A method and apparatus is provided for encoding a signal within a radio frequency transmitter 10. The method includes the steps of dividing an information bit stream into a set of successive representations of constellation symbols, each with a symbol interval and finite impulse response filtering each constellation symbol of the set of successive representations of constellation symbols to produce at least one filtered symbol sample per symbol interval. The method further includes the steps of vector adding the at least one filtered symbol sample per symbol interval of the set of successive representations of constellation symbols to produce an output constellation symbol. An apparatus is provided with means for implementing the steps of the method. Included within the apparatus is a low-overhead means of selecting modulation method.

Encoding method for constellation symbols of an RF transmitter

An automatic frequency control loop structure utilizes a dual selection automatic frequency control unit which is coupled to a differential phase unit and a coherent phase unit to provide a frequency corrected received signal output for efficient tracking of frequency offset drift; and a much lower probability of loss of automatic frequency control loop lock. Thus, a signal from a coherent carrier recovery process provides additional benefit by utilization in adjusting frequency offset tracking performance.

An apparatus and method for symbol timing tracking has a decimation index input (42). The decimation index (42) is connected to an upper threshold limiter (44) and a lower threshold limiter (46). The upper threshold limiter (44) is connected to an upper shift register (48). A plurality of cells (52) in the upper shift register (48) are connected to a majority vote logic circuit (54). The majority vote logic circuit (54) is connected to a symbol clock time base (56) and a clocking and clearing control circuit (62). The clocking and clearing control circuit (62) has a clock enable output and a clear signal connected to the upper shift register (48). The lower threshold limiter (46) is connected to a lower shift register (58) that is connected to a second majority vote logic circuit (60).

Method and apparatus for symbol timing tracking

The present invention provides for economical predictive symbol timing estimation in a digital receiver by reducing gate count and current drain. The invention also reduces the processing delay. The predictive symbol timing estimation method (300) and device (200) are applicable to any digital radio system which transmits on a continuous or semi-continuous basis.

Device and method for efficient timing estimation in a digital receiver

A method and apparatus is provided for generating Walsh codes. A first group of address signals is generated. Subsequently, inversion control signals are generated by logically gating the first group of address signals with a second group of address signals. Finally, a Walsh code is produced by inverting elements of a predetermined vector in accordance with the generated inversion control signals.

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Algonquin, IL, United States of America

David Paul Gurney