Mitsubishi Denki Kabushiki Kaisha

Apricot Computers Limited

David P Wright

Yoichi Nakamura

Kunio Takahari

Toshikazu Yokoi

Nigel Bruce

Colin Hough

Satoshi Kobayashi

Junichi Ishikawa

A symmetric multiprocessor system connecting a plurality of CPUs by a common bus initializes itself while defective CPUs are set aside to use only the remaining CPUs when the power is turned on, thereby maintaining the predetermined CPU numbers and giving a minimum influence with the existing software thereof. The multiprocessor system includes an identifier setting register to designate in a predetermined order the CPU numbers only to normal CPUs, and a reset controller to cut off the defective CPUs from the common bus. The multiprocessor system can automatically start re-setting up where the defective CPUs are detected during the processing of setting-up based on the time-out detection, can release an abnormal state of the hardware, and can control the setting-up processing in use of any CPU based on the level of a reset status input port and contents of a reset information register.

Method and apparatus for initializing a multiprocessor system while

Apparatus to supplement cache controller functionality in a memory store

Growing community of inventors

Birmingham, United Kingdom

David P Wright