Unisys Corporation

David P Williams

Stephen Sutter

Kelvin S Vartti

Douglas A Fuller

Robert Marion Malek

James A Williams

Robert H Andrighetti

Chad M Sonmore

Marshall R Dew

Robert Norman Anderson

Howard Huy P Tran

Jason D Lanfield

A system and method for performing dynamic partitioning operations within a data processing system is disclosed. According to one embodiment, the current invention provides a system that allows an unit to be added to an executing data processing partition. The partition may include a shared resource that is receiving requests from other units that are already included within the partition. The inventive system includes means for programmably enabling the unit to the shared resource. Once the unit is so enabled, the system synchronizes the request arbitration being performed by this unit with the arbitration activities occurring within other units requesting access to the shared resource. This synchronization process prevents two units from attempting to simultaneously access the shared resource.

System and method to support dynamic partitioning of units to a shared resource

A manner for judiciously snooping or otherwise monitoring bus operations associated with maintaining cache or other memory coherency in a computing system. A bus snoop information storage mode is established that identifies information pertaining to the bus snoop operations used to maintain memory coherency. The bus snoop information storage mode is selectable, relative to possible other modes. When the bus snoop information storage mode is activated, the information pertaining to the bus snoop operations occurring in connection with bus snoop stall cycles is disregarded, while the current state of the information pertaining to the bus snoop operations upon completion of the bus snoop operations is stored.

System and method for selectively storing bus information associated with memory coherency operations

A computing system with a mode-selectable bus interface. In one embodiment, the computing system includes a system bus, a processor coupled to the bus via an interface unit, and a controller coupled to the bus. The system bus implements one of a first and a second system bus protocols. The interface unit is compatible with the first system bus protocol in a first selectable mode and the second system bus protocol in a second selectable mode, and the controller is compatible with one of the system bus protocols. A mode register is coupled to the interface unit, and the interface unit selects the first mode responsive to a first value of the mode register and selects the second mode responsive to a second value of the mode register. A scan controller is coupled to the mode register for scanning a value into the mode register.

Dual mode capability for system bus

A system and method for selectively collecting information within logical modules of the computing system, where the content collected and the collection periods are dynamically controllable to accurately target the most relevant information. One of a plurality of information storage modes is dynamically selected, where each of the information storage modes identifies a different set of information from the plurality of logical segments that is to be stored. At least one of a plurality of data collection periods is dynamically selected, where the data collection periods define temporal windows in which storage of the designated set of information is enabled. The designated set of information identified by the designated information storage mode is stored only during the designated data collection period.

Method for controlling and collecting information in a data processing system

A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated if the associated data signals are considered 'leaky'. These data signals are flushed from the cache memory after a predetermined delay has occurred. The delay is provided to allow the IP to complete any subsequent requests for the same data before the flush operation is performed, thereby preventing memory thrashing. Pre-fetch logic may also be provided to pre-fetch the data signals associated with the requests. In one embodiment, the rate at which data signals are flushed from cache memory is programmable, and is based on the rate at which requests are processing for pre-fetch purposes.

Delayed leaky write system and method for a cache memory

A system and method for providing speed-regulated data transmission between two synchronous systems in different clock domains. A first synchronous circuit includes a memory device, and a second synchronous circuit includes one or more data-requesting devices. The first synchronous circuit operates at a greater clock speed than the clock speed of the second synchronous circuit. A read request buffer queues read request signals from the data-requesting devices, and outputs one of the read request signals to the memory device. A pulse generator receives the read request signal which was output from the queue, and generates a plurality of signal pulses in response thereto. Each of the pulses occurs at a different predetermined time from the occurrence of the read request signal. One of the pulses is selected to be the read acknowledge signal, and assertion of the read acknowledge signal allows the read request buffer queue to output another read request signal.

System and method for controlling data transmission rates between

A system for use in transferring data packets across different clock domains using an input data register for receiving a block of data packets with the input data register and a plurality of interface registers located in the first clock domain for transferring a block of data packets from the input register to a second clock domain in response to a request signal with the system prioritizing the transfer of multiple data packets within the block of data packets by length in order to transfer the longer word packets first and the shorter word packets last with the shortest word packets within the block bundled together and simultaneously transferring across an asynchronous interface.

System for data transfer across asynchronous interface

A system and method for transmitting commands from one or more input/output devices to a memory is provided. An identification tag is appended to each command to define the command as either a read or write command. The read commands are separated from the write commands based on the state of the identification tag, and the read and write commands are separately queued. The read commands are stored in a first command queue, and the write commands are stored in a second, separate, command queue. The read commands in the first command queue are successively transferred to the memory upon completion of the current memory read function, and the write commands in the second command queue are successively transferred to the memory upon completion of the current memory write function. The transfer of the read and write commands is independent.

Optimized input/output memory access request system and method

A method and apparatus for efficiently reading a day clock and storing the value into main storage. An advantage is that the memory storage command can request the main storage control to read a current day clock value and store the value into a main storage location specified by the requesting processor while allowing the requesting processor to continue processing other commands. A further advantage is that the requesting processor does not have to wait for the return of a day clock value or the generation of a main storage write request which may reduce the number of main storage I/O bus requests and bus transfer cycles over that normally required to transfer the day clock value to the requesting processor and then back to main storage.

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Mounds View, MN, United States of America

David P Williams