Ncr Corporation

Lsi Logic Corporation

David P Steele

Harold S Crafts

3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.

Method and apparatus for self correcting parallel I/O circuitry

A transient immune bistable input buffer circuit. The circuit comprises a filter connected between an input and a reference voltage terminal to the circuit for reducing the sensitivity of the circuit to a voltage transient on the terminal.

Transient immune input buffer

A buffer circuit with controlled output switching rate suitable to suppress ground or power supply line voltage spikes attributable to current surges. The voltage driving the gate electrode of the selected CMOS inverter output transistor is controlled in rate of rise using three parallel connected sources of charging current. The first source of current is enabled immediately following the step input signal to provide a relatively high initial rate of current flow and corresponding voltage rise on the gate electrode of the output transistor, but is self-disabled at approximately half the supply voltage by threshold loss and body effect on the transistor supplying the first source of current. The succeeding time interval is characterized by a slow rate of rise of the output transistor gate voltage attributable to a small but continuous source of current to the output transistor gate electrode node. The concluding interval is characterized by a high rate of current flow to the gate electrode node, but is enabled by feedback responsive to having the output node approach the final logic level. The circuit is suitable for suppressing both ground line and power supply line voltage spikes, and is further capable of being implemented in a tri-state configuration with minimum added complexity.

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Colorado Springs, CO, United States of America

David P Steele