Tandem Computers Incorporated

Compaq Computer Corporation, Inc.

Intel Corporation

David P Sonnier

William J Watson

David J Garcia

William P Bunton

Robert W Horst

John C Krause

William Edward Baker

Daniel L Fowler

Linda Ellen Zalzala

Geoffrey I Iswandhi

Frank A Williams

Richard W Cutts, Jr

John D Coddington

William F Bruckert

Susan S Meredith

Paul N Hintikka

Curtis Willard Jones, Jr

Stephen G Low

James Stevens Klecka

Gary F Campbell

John Michael Brown

Douglas E Jewett

Steven C Meyers

Patricia L Whiteside

David B Brown

Randall G Banton

Stephen R Bissell

Daniel D Gunn

David L Aldridge

Juergen Beck

Carl W Kagy

Stephen H Miller

Kenneth H Porter

Barry Lee Drexler

Harry Frank Elrod

Michael P Simpson

H David Mattson

Patracia L Whiteside

Wiliam P Bunton

David Joseph Kinkade

Self-checked, lock step processor pairs

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Method of data communication flow control in a data processing system

Detecting and isolating errors occurring in data communication in a

A circular queue is asynchronously accessed and managed by two separate processing elements. Each data element is added to the queue together with a zero data element that both marks the tail of the queue and signifies that the queue is empty. Data elements are removed from the queue in the order in which they were stored (first-in-first-out) and a manner that allows multiple, concurrent access to the queue. When the queue is accessed to remove a data element the element is first tested. If it is non-zero, the removal process continues; if zero, the queue is considered empty. The management of the queue permits dynamic re-sizing (i.e., making the queue larger or smaller) while data elements are being added and/or removed.

Method of management of a circular queue for asynchronous access

A multiple processing system, comprises at least a pair of processor units communicatively connected to a number of peripheral devices through a network that includes routing devices interconnected to route information in the form of message packets sent between the processor units and peripheral devices. Data describing the topographical interconnections of the system elements is maintained with the system. A service processor accesses the data, determines therefrom the topographical interconnections forming the network, assigns addresses/identifications to the system elements, and configures the router devices to establish the most direct routes between system elements for message packets sent on the network.

Method and apparatus for configuring routing paths of a network

A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Storage access validation to data messages using partial storage address

A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.

Network message routing using routing table information and supplemental

Apparatus for detecting divergence between a pair of duplexed,

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Method of synchronizing a pair of central processor units for duplex,

A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for providing two levels of arbitration to select one of the inputs for data communication to an output. The first (lower) level of arbitration bases selection upon a round-robin order; the second (higher) arbitration level selects inputs based upon an indication from an input of an undue wait for access to the output over a period of time. Each input is provided a modulo-N counter, and a digital counter. Each time an input contends for access to an output and loses to selection by the output to another input, the modulo-N counter is incremented by an assigned value for that input. When N is exceed without access, the digital counter is incremented. The content of the counter operates to force the high-level arbitration.

Routing arbitration for shared resources

A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs based upon a comparison of accumulated bias values that can change over time when an input is kept waiting. Each input is provided an assigned bias value from which is developed the accumulated bias value that is compared with that of other inputs arbitrating for access to an output. The output selects one of the inputs, based upon the comparison, and the accumulated bias value of the selected input is diminished by the sum of the assigned bias values of the inputs participating in the arbitration, but not selected, while the accumulated bias values of the other participants are each increased by their corresponding assigned bias values. Thereby, numbers of inputs having data destined for the same output will have their chance of gaining access to the output increased the longer they wait; conversely, inputs which do gain access have their chances for immediate subsequent access decreased in favor of allowing other inputs access.

Latency reduction and routing arbitration for network message routers

The present invention provides a mechanism for initial execution of software code by a processor in a multiprocessor system. In the preferred embodiment, the multiprocessor system has registers implemented at a reset vector location in a processor. The registers are first loaded with a sequence of software code, and then a first instruction loop is implemented with that software code. The processor is then released from a reset state, and the first instruction loop is executed. This first instruction loop is capable of being executed for an indefinite length of time, and it can execute software instructions on a periodic basis. The first instruction loop is then modified into a second instruction loop. The first and second instruction loops have at least one different instruction. The processor within the system of multiple processors is thus initialized.

Spoon-feed initialization in a multiprocessor system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.

Interrupt message delivery identified by storage location of received

A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.

Method for verifying responses to messages using a barrier message

Growing community of inventors

Austin, TX, United States of America

David P Sonnier