Xilinx, Inc.

Bell Helicopter Textron Inc.

Textron Innovations Inc.

David P Schultz

F Erich Goetting

Steven P Young

Vasisht Mantra Vadi

Lawrence C Hung

Carlos Alexander Fenny

Jennifer Wong

Anthony J Collins

Ian A Swarbrick

Weiguang Lu

Warren E Cory

John D Logue

John E McGrath

Ahmad R Ansari

Suresh M Menon

Venu M Kondapalli

Jun Liu

Richard William Swanson

Roman Iwanczuk

David Robinson

Bernard J New

Martin L Voogel

James M Simkins

Raymond Kong

Alvin Y Ching

Philip D Costello

John M Thendean

Scott O Frake

Jason R Bergendahl

Jian Tan

Anna Wing Wah Wong

Eunice Y D Hao

Sourabh Goyal

Atul V Ghia

Neil G Jacobson

Rafael C Camarota

Stephen M Douglass

Paige A Kolze

Mehul R Vashi

Christopher D Ebeling

Shidong Zhou

Brian Von Herzen

Wilson Kaming Yee

Subodh Kumar

Jane W Sowards

Nigel G Herron

Felix Burton

Edward S McGettigan

Robert Paul Reynolds

Bradley K Fross

Tao Pi

Sanford L Helton

Hao Yu

David B Squires

Karthy Rajasekharan

Jing Jing Chen

Joseph B Diller

Herve Alexanian

Michelle Zeng

Kin Yip Sit

Michael Tsivyan

Adrian M Hernandez

Wenyi Song

James L McManus

Jeffrey Cuppett

Elessar Taggart

Kusuma Bathala

Ian L Price

David A Curd

Priyanka Agrawal

Corey Dickman

Jon A Brunetti

Corey J Dickman

Mikael Palczewski

Wade K Peterson

Rodney Cahoon

Nagendra Donepudi

Max Heimer

Darrel B Bryan

An aircraft thermal hydraulic active-warming system includes an active thermal-warming valve interoperably coupled between a hydraulic pressure line and a hydraulic low-pressure return line and a hydraulic actuator arranged in parallel with the active thermal-warming valve between the hydraulic pressure line and the hydraulic low-pressure return line.

Thermal hydraulic active warming system

An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

Clocking architecture for communicating synchronous and asynchronous clock signals over a communication interface

An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

Clocking architecture for communicating clock signals having different frequencies over a communication interface

Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

Register integrity check in configurable devices

Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

Distributed configuration of programmable devices

An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.

Programmable device configuration memory system

Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

Tracing status of a programmable device

Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.

Configuring programmable logic region via programmable network

Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

Retaining memory during partial reconfiguration

Examples described herein provide for an electronic circuit, such as a System-on-Chip (SoC), having a Network-on-Chip (NoC). The NoC is configurable and has capabilities to be partially reconfigured. In an example, a NoC on an integrated circuit is configured. Subsystems on the integrated circuit communicate via the NoC. The NoC is partially reconfigured. A first subset of the NoC is reconfigured during the partial reconfiguration, and a second subset of the NoC is capable of continuing to pass communications uninterruptedly during the partial reconfiguration. After the partial reconfiguration, two or more of the subsystems communicate via the first subset of the NoC.

Partial reconfiguration for Network-on-Chip (NoC)

Method, apparatus and computer-readable medium for providing a partial reconfiguration of a reconfigurable module are described. In one example, a method reads a netlist for a design of a circuit comprising a reconfigurable module and sets the reconfigurable module to a first region. The method then generates a second region that encompasses the first region and places the design with the first region. The method routes the design with the second region and generates a partial bitstream for the reconfigurable module.

Extend routing range for partial reconfiguration

A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.

Circuit for and method of configuring and partially reconfiguring function blocks of an integrated circuit device

A peripheral interconnect for configuring slave endpoint circuits, such as may be in a configurable network, in a system-on-chip (SoC) is described herein. In an example, an apparatus includes a processing system on a chip, a circuit block on the chip, and a configurable network on the chip. The processing system and the circuit block are connected to the configurable network. The configurable network includes a peripheral interconnect. The peripheral interconnect includes a root node and a plurality of switches. The root node and the plurality of switches are connected in a tree topology. First branches of the tree topology are connected to respective slave endpoint circuits of the configurable network. The slave endpoint circuits of the configurable network are programmable to configure the configurable network.

Peripheral interconnect for configurable slave endpoint circuits

A circuit for routing data in an integrated circuit device is described. The circuit comprises an input/output port; an interface circuit coupled to the input/output port and configured to receive data, the interface circuit comprising a selection circuit enabling the selection of the data and a predetermined value; and a control circuit coupled to control the selection circuit; wherein the control circuit holds the input/output port at the predetermined value during a partial reconfiguration of the integrated circuit device in response to a control signal. A method of configuring a circuit for routing data in an integrated circuit device is also described.

Circuit and method for ensuring a stable IO interface during partial reconfiguration of a reprogrammable integrated circuit device

A multi-chip structure that implements a configurable Network-on-Chip (NoC) for communication between chips is described herein. In an example, an apparatus includes a first chip comprising a first processing system and a first configurable NoC connected to the first processing system, and includes a second chip comprising a second processing system and a second configurable NoC connected to the second processing system. The first and second configurable NoCs are connected together via an external connector. The first and second processing systems are operable to obtain first and second information from off of the first and second chip and configure the first and second configurable NoCs based on the first and second information, respectively. The first and second processing systems are communicatively coupled with each other via the first and second configurable NoCs when the first and second configurable NoCs are configured based on the first and second information, respectively.

Multi-chip structure having configurable network-on-chip

Growing community of inventors

San Jose, CA, United States of America

David P Schultz