Crosspoint Solutions, LLC

Gte Government Systems Corporation

Synopsys, Inc.

Qda, Inc.

Cadence Design Systems, Inc.

David P Marple

Laurence H Cooke

Michael Francis O'Connor

Randall L Jackson

Abbas A El Gamal

Justin M Reyneri

The present invention relates to layouts with geometrical objects, and more particularly, to a system and method for compacting layouts in two dimensions simultaneously. In an embodiment, the system and method of the present invention are applied to IC layouts. The present invention provides for compacting layouts in two dimensions at once without depending on expensive methods such as Branch and Bound. As a result, in an embodiment, the present invention can be applied to large layouts in much the same way as conventional, one dimensional compaction systems and methods. The present invention also provides for compacting hierarchical layouts in two dimensions at once while preserving the complete hierarchy.

Two dimensional compaction system and method

An FPGA includes primary resources and redundant resources. To program an FPGA to perform a desired function, a pattern of programmable elements to be programmed that takes advantage of primary resources only is first prepared. This pattern is then modified responsive to previously obtained information about defects within the FPGA. The modified pattern takes advantage of redundant resources as direct or indirect substitutes for FPGA elements rendered unusable by defects. The FPGA is programmed in accordance with the modified pattern.

FPGA redundancy

Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.

CAD and simulation system for targeting IC designs to multiple

A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.

Field programmable gate array

A noise threshold estimating method for use in a high signal density environment defines a noise threshold level for a plurality of frequency divided channels such that X number of said channels will be defined as being active channels and the remaining channels as being inactive. Using a novel closed loop feedback technique to define a noise threshold level, the noise threshold estimator first compares the signal level of each incoming channel with an analog threshold voltage. A logic device counts the number of active channels and then scales that number according to a predetermined scaling function. The scaled binary number is added with the noise threshold level from the previous clocked interval to define a new noise threshold level. This binary noise threshold level is converted into an analog voltage and feedback to the feedback input of the noise comparison devices to be compared with the signal level of each incoming channel.

Noise threshold estimating method for multichannel signal processing

A noise threshold estimator for use in a high signal density environment defines a noise threshold level for a plurality of frequency divided channels such that X number of said channels will be defined as being active channels and the remaining channels as being inactive. Using a novel closed loop feedback technique to define a noise threshold level, the noise threshold estimator first compares the signal level of each incoming channel with an analog threshold voltage. A logic device counts the number of active channels and then scales that number according to a predetermined scaling function. The scaled binary number is added with the noise threshold level from the previous clocked interval to define a new noise threshold level. This binary noise threshold level is converted into an analog voltage and fedback to the feedback input of the noise comparison devices to be compared with the signal level of each incoming channel.

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Palo Alto, CA, United States of America

David P Marple