Hewlett Packard Enterprise Development LP

Other

David P Kopp

Karl Joseph Bois

Elene Chobanyan

Benjamin Toby

James David Stewart

Steven Martin

One aspect provides a printed circuit board (PCB). The PCB includes a transmission line to transmit signals of a desired frequency, a first stub coupled to the transmission line at a first location, and a second stub coupled to the transmission line at a second location. The first stub is to filter out signals of a first frequency, the second stub is to filter out signals of a second frequency, and the first and second stubs are positioned such that an insertion loss of the transmitted signals of the desired frequency is substantially minimized.

Double stub transmission line for suppression of harmonics

A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.

AC-coupling structure in electrical cabled interconnect

A multiple-layer circuit board has a signaling layer plane, an exterior layer plane, and a ground layer plane. A pair of differential signal lines implemented as strip-lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. A dual slot common mode noise filter may be etched within the ground layer and may include a first U-shaped etching pair comprising a first U-shaped etching and a second U-shaped etching opposing the first U-shaped etching within the ground layer plane.

Dual slot common mode noise filter

A faucet control apparatus having a handle, a ring member and optionally protrusions. The handle has a proximal and a distal end. The ring member is positioned proximate the proximal end thereof. The ring member has an inner perimeter which defines an opening. The protrusions include one or more outer protrusions optionally extending from the ring member spaced apart from the handle member.

Faucet control aid apparatus

An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slicer by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a number of total bits and a number of erroneous bits based on the digital output signal and calculating a two-sided bit error ratio frequentist confidence interval (FCI) size from the measured bit error ratio. The measured bit error ratio is output in response to the two-sided bit error ratio FCI being less than or equal to a two-sided bit error ratio interval target size.

Bit error ratio tests with two-sided bit error ratio frequentist intervals

An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slices by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a bit error ratio based on the digital output signal and determining a confidence level for the measured bit error ratio, and in response to the determined confidence level equaling or exceeding a specified value, designating a current value of the measured bit-error ratio as the expected bit error ratio for the corresponding time-voltage slice and ending the test operation.

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Ft. Collins, CO, United States of America

David P Kopp