Intel Corporation

Motorola Corporation

David P DiMarco

Jeffrey L Miller

Michael J Allen

Jonathan H Liu

James W Conary

Douglas D Smith

James W Nicholes

R Kenneth Hose

A tag RAM is coupled to an address bus that is adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the address bus and the memory section. The tag RAM further includes a selection module coupled to the address bus and coupled to the comparator. The selection module selects one or more bits of the address field as tag field bits depending on the width of the address field and the size of the cache memory coupled to the tag RAM.

Tag RAM with selection module for a variable width address field

A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.

Detecting states of signals

Reducing timing variance of signals from an electronic device

Method and apparatus to monitor a characteristic associated with an electronic device

An apparatus and method for enabling multiple sense amps in a burst read memory is described. The sense amps are divided into two sets which are then enabled at slightly different times. The time difference is set so that a maximum power consumption experienced when the sense amps are enabled is reduced significantly, but the effect on the total time needed to read the data is not increased.

Sense amplifier timing method and apparatus for peak power reduction

A CPU is coupled to the cache memory over a system bus having a width of 64 data bits. The cache memory is organized into a left array and a right array, with data bits stored as lines of data wherein each line is comprised of 256 data bits defined into four data 'chunks' of 64 bits each. Each memory read access by the CPU to the cache results in a complete line of data to be read in the cache. The chunks comprising the line of data are coupled over an internal cache bus to a 'chunk' multiplexor. The chunk multiplexor stages the data chunks in an order defined by the CPU, and sequentially send the data chunks over the system bus to the CPU. The chunks are organized as high and low order chunks. The multiplexor includes a first multiplexor for receiving the high order chunks and a second multiplexor for receiving the low order chunks. Latches are provided which are coupled to the first and second multiplexors to receive the high order chunks upon the receipt of a first clock signal, and the low order chunks upon the receipt of a second clock signal. Enabling signals are provided to the latches such that the high order and low order chunks are coupled to the system bus in a sequential order which is determined by the CPU.

Cache memory having a multiplexor assembly for ordering output on a data

An improved cache memory architecture is disclosed, having particular application in a cache having static random access memory (RAM). In a typical static RAM memory utilized as a cache, the cache has the requirement that it must access many more bits than is required for selection. A single wordline of the RAM may span an entire memory array, and the activation of the entire wordline results in many more bitlines activated than will actually be selected by the Y decoder. As a result, power is wasted. The present invention provides a cache memory in which even and odd columns are segregated, wherein the even addressed columns may be placed in a first set (0) and the odd addressed columns in a second set (1). The wordline decode includes two wordlines per row rather than the typical single wordline in prior art systems. The first wordline corresponds to the 'even' wordline, and the second wordline corresponds to the 'odd' wordline (set 1). Only one wordline is activated at any time to save power. The wordline decoder of the present invention utilizes an address bit (for example, the low order bit) to select either the driver for the columns corresponding to the even wordline or to the odd wordline. Although the present invention requires additional drivers, only one driver is activated at any one time. It has been found that the architecture of the present invention provides a total power savings in a read operation approaching fifty percent.

Power saving architecture for a cache memory

A circuit for converting an input signal derived from a low voltage power supply to an output signal derived from a high voltage power supply is disclosed. A driver circuit and a conversion circuit simultaneously receive the low voltage input signal. The driver circuit changes states when the input signal transitions and the output signal switches accordingly. The conversion circuit simultaneously generates a high voltage signal that causes a decoupler circuit to eliminate any DC leakage through the driver circuit. The driver circuit utilizes a bipolar transistor to increase drive capability.

BiNMOS driver circuit with integrated voltage supply conversion

Sense amplifier timing method and apparatus for peak power production

A configurable decode circuit (11) having a plurality of inputs (12), a clock input (13), an output (14), and an output (16) is described. The configurable decode circuit (11) is a nor type decoder configurable to different address widths. A latch (17) stores the decode results. A bias circuit (29) enables the configurable decode circuit (11) starting a decode cycle. A differential input stage is coupled between the latch (17) and bias circuit (29). One side of the differential input stage comprises a plurality of transistors (23) coupled in parallel. Each control electrode of the plurality of transistors (23) is coupled to a respective input of inputs (12). The other side of the differential input stage comprises a transistor (28) coupled between the latch (17) and the bias circuit (29). A control electrode of the transistor (28) is coupled to common first electrodes of the plurality of transistors (23).

Decoder and latching circuit with differential outputs

A memory circuit uses sense amplifiers to amplify a low level differential data signal from the memory cells to full logic levels. A first sense amplifier converts the low level differential data signal to an intermediate differential voltage level at first and second nodes during the read cycle. A second sense amplifier converts the intermediate differential voltage level to the full logic level. The first and second sense amplifiers are powered down after sensing is complete. A circuit drives the intermediate differential data signal to an equilibrium voltage level when the sensing is complete to reduce the power up delay time of the second sense amplifier and thereby increase the operating speed of the memory circuit. A latching circuit is synchronized with the power down of the first sense amplifier to latch the output logic level at the end of the read cycle.

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Hillsboro, OR, United States of America

David P DiMarco