Juniper Networks, Inc.

Silicon Graphics, Incorporated

Juniper Networs, Inc.

David P Chengson

Edward C Priest

Ranjeeth Doppalapudi

Jaya Bandyopadhyay

Matthew A Tucker

Ali Mira

Unmesh Agarwala

John C Manton

Alan D Foster

Joel Darnauer

William L Schmidt

Chang-Hong Wu

Santosh Kumar Pappu

Edward C Chang

David James Ofelt

Bhavesh Patel

Hansel A Collins

Granthana Kattehalli Rangaswamy

Scott W Alvarez

Victor Do

Robert A Conrad

Techniques are described for a method for detecting a fault. The method includes receiving, by a receiving electronic device, via a differential pair transmission line, from a transmitting electronic device, an electrical signal. The method further includes converting, by a receiving (Rx) serializer/deserializer (SerDes) operating at the receiving electronic device, the received electrical signal into a received digital electrical signal. The method further includes, determining, by one or more processors, an electrical signature of the received electrical signal from the received digital electrical signal when the received electrical signal is received by the receiving electronic device. The method further includes determining, by the one or more processors, based on the electrical signature, a position of a fault between the receiving electronic device and the transmitting electronic device. The fault causes the received electrical signal to be different than the transmitted electrical signal.

Electrical signature fault detection

A printed circuit board (PCB) assembly may include a component capable of sending or receiving high-speed differential signal pairs, a package that is connected to the component, and a PCB connected to the package. The PCB assembly may be used to support a first high-speed differential signal pair that includes a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through the PCB assembly. A set of interconnects may be used to intelligently route the first differential signal pair within the package and/or within the PCB. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal and a second interconnect to route the second differential signal toward the particular differential signal.

Grid array pattern for crosstalk reduction

An apparatus may include via pads and grid array pads associated with facilitating a connection through a package and to a component, and vias that are electrically connected to the via pads, wherein the vias are used to support high-speed differential signal pairs that are capable of causing crosstalk onto other high-speed differential signal pairs while propagating through the package. The apparatus may include interconnects that electrically connect the vias to the grid array pads, and that are capable of routing the high-speed differential signal pairs in a way that offsets the crosstalk that the high-speed differential signal pairs are capable of causing while propagating through the package. The apparatus may include additional interconnects that electrically connect the vias to additional vias that are to be used to facilitate routing the high-speed differential signal pairs to the component, without the high-speed differential signal pairs propagating through a printed circuit board.

In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.

Placement of vias in printed circuit board circuits

In an example of this disclosure, a method may include receiving, by a bit error location analyzer, a split information signal at a second data rate derived from an information signal at a first data rate. In this example, the second data rate is less than the first data rate, and the bit error location analyzer may be incapable of performing error analysis at the first data rate The method may include performing error analysis, by the bit error location analyzer, on information represented by the split information signal. In some examples, performing error analysis may include comparing the information represented by the split information signal to an information seed to determine a plurality of bit error locations in the information represented by the split information signal relative to the information seed.

Systems and methods for error detection and correction

In general, techniques are described that insert one or more bits into a digital bit stream to maintain an overall transition density in the digital bit stream. Maintaining the overall transition density facilitates the generation of a recovered clock by a phase-locked loop (PLL) circuit of a receiver. For example, when a data transition ratio for a portion of the digital bit stream is less than a desired data transition ratio, the techniques insert additional bits to increase the overall transition density of the digital bit stream.

Digital bit insertion for clock recovery

A network device includes a group of high speed redundant transmission lines and a switch. The switch is configured to select one of the high speed redundant transmission lines. The switch causes reflections and frequency dependent dispersions in the selected high speed redundant transmission line. The network device further includes a transmitting device that is configured to adjust signals transmitted over the selected high speed redundant transmission line so as to reduce the reflections and frequency dependent dispersions.

Systems and methods for reducing reflections and frequency dependent dispersions in redundant links

A device provides a time domain reflectometry (TDR) or a vector network analyzer (VNA) test signal to a via test area provided on a printed circuit board (PCB), where the via test area includes vias and via stubs formed in the vias. The device also receives a reflected signal from each via in the via test area of the PCB, and compares the reflected signal from each via to a minimum impedance threshold. The device further provides, for display, an indication of passing for the PCB, when the reflected signals from the vias are greater than the minimum impedance threshold.

Testing vias formed in printed circuit boards

A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Low latency serial memory interface

A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

Multi-interface compatible bus over a common physical connection

An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter.

Error-free startup of low phase noise oscillators

A high speed transmission system transfers data streams over a plurality of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and phase is embedded in the transmitted data. At the receiving end, a clock signal of an appropriate frequency and phase is generated. The new clock signal is used to sample and reconstruct the original data streams.

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Aptos, CA, United States of America

David P Chengson