Microchip Technology Inc.

David Otten

Joseph Harry Julicher

Sean Steedman

James E Bartling

D C Sessions

Yong Yuenyongsgool

Prashanth Pulipaka

Jacobus Albertus Van Eeden

Naveen Raj

Daniel Butler

Prasanna Surakanti

An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.

Method and apparatus for split burst bandwidth arbitration

A high resolution digital-to-analog converter comprises a programmable n-bit current digital-to-analog converter (IDAC), an m-bit programmable counter/timer, an integrator that converts the IDAC constant current charging a capacitor over time into an a precision (high resolution) analog voltage, and a sample and hold circuit for storing the precision analog voltage. The constant current from the IDAC is applied to the integrator for a time period determined by the programmable counter/timer, then the sample and hold circuit will sample the final voltage on the capacitor and store it as an analog voltage. The analog voltage resolution of this high resolution digital-to-analog converter is n+m bits or binary 2. In addition, a plurality of sample and hold circuits may be utilized for maintaining a plurality of analog output voltages.

Current-time digital-to-analog converter

Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an integer multiple of a reference oscillator. The clock speed will be proportional to the frequency multiplication of the PLL when the faster clock speed is selected. A multiplexer is used to switch between different frequency sources, and a timer can be used to insure stable operation of the PLL. A status configuration register has status and control bits for indicating and controlling operation of the clock speed control. A universal serial bus (USB) device can operate at a slower clock with reduced operating voltage, and at a faster clock with increased operating voltage.

Digital system having selectable clock speed based upon available supply voltage and PLL configuration register settings

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Chandler, AZ, United States of America

David Otten