Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

David O'Sullivan

Thorsten Meyer

Klaus Reingruber

Andreas Wolter

Markus Brunnbauer

Christian Geissler

Sven Albers

Jan Proschwitz

Frank Zudock

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Method of manufacturing a semiconductor device including removing a relief layer from back surface of semiconductor chip

A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.

Chip arrangement with a recessed chip housing region and a method for manufacturing the same

Chip with encapsulated sides and exposed surface

A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Semiconductor device with chip having low-k-layers

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Sinzing, Germany

David O'Sullivan