Lsi Logic Corporation

Seagate Technology Incorporated

Micron Technology Incorporated

Lsi Corporation

David O Sluiter

Robert Wayne Moss

Russell B Stuber

Christopher M Giles

David G Springberg

Ara Patapoutian

Darren Duane Neuman

Young Pil Kim

Christopher D Paulson

Timothy D Thompson

Jeffrey John Pream

Peter Korger

Donald Preston Matthews, Jr

Nicholas Odin Lien

Mark Jon Kwong

David A Thomas

Alan R Gilchrist

Mark Buchanan

Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold. The processing device further writes the second write data from the internal SRAM device as a second programming unit to the one or more NVM devices.

Two-stage hybrid memory buffer for multiple streams

Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.

The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.

Multi-dimentional data randomization

A method for discarding perpetually-rejected packets in a fabric-based interconnect having a reliable physical layer is disclosed. A transmitting component keeps a count of the number of negative acknowledgements (NAKs) it receives from the receiving component for packets the transmitting component sends. If the transmitting component receives a number of consecutive NAKs for the same packet that exceeds some pre-determined threshold, the packet is not resent, but is, instead, treated as having been acknowledged, and subsequent packets are allowed to be transmitted. Higher-level processes are then notified of the problem so as to allow the error to be dealt with at a higher level, but without obstructing the flow of packets on the physical layer.

Method for discarding corrupted data packets in a reliable transport fabric

Method and apparatus for compressing data. In accordance with various embodiments, an input string of data bits is received and arranged into fixed-sized chunks. Multiple successive chunks of the input string are compared to previously received chunks of the input string during a single clock cycle. At least two alternative encoding solutions are identified based on matches obtained during said comparison. The input string is compressed to form a compressed output string using a selected one of the at least two alternative encoding solutions that achieves a fewer number of bits in said output string.

Evaluating alternative encoding solutions during data compression

An embodiment of a method for compressing data includes variable length coding one or more values of control codes generated from dictionary coding the data, wherein the control codes comprise literals and indices, wherein each index comprises a length value and a pointer to previously read in data. An embodiment of a system for losslessly compressing input data includes a modeler operable to determine whether a set of input data matches prior input data, an encoder operable to generate control codes including one or more literal control codes and one or more index control codes, wherein each index control code includes a pointer to a location in the input data and a length value indicating a number of bytes to copy from the location, and wherein the length value is variable length coded.

System and method for lossless data compression

An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

Long path at-speed testing

A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Apparatus for arbitrating non-queued split master devices on a data bus

Ownership of a peripheral bus between a peripheral device and a plurality of master devices is assigned to one of the master devices. Each master device has an associated controller for controlling the peripheral device via the peripheral bus. Communication occurs without impediment between the master device and its controller that have ownership of the bus, thereby conducting transactions via the peripheral bus and peripheral device. Communication with the master device and controller not having ownership is blocked, making the controller look busy to the master device and making the master device look idle to the controller. The ownership is assigned to the master/controller pairs using an arbiter arrangement.

Process and apparatus for managing use of a peripheral bus among a plurality of controllers

A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter is not conducting a transaction. If the second device desires use of the bus, the slave arbiter sends a request to the master arbiter, which asserts an acknowledge signal for as long as the first device has ownership of the bus, and at least as long as a timeout of the first device. The master arbiter de-asserts its acknowledge signal when the first device ceases ownership of the bus. The slave arbiter is responsive to the de-assertion of the acknowledge signal to assert bus ownership to the second device. When the second device transaction is completed, its request signal is de-asserted to the master arbiter, causing the master arbiter to re-assert the acknowledge signal. Failure to receive a de-asserted acknowledge signal causes the slave arbiter to move to the next state.

Four-phase handshake arbitration

An electronic bus architecture for supporting posting of read requests by multiple master devices to multiple slave devices. Sideband signals added to the underlying master bus architecture permit slave devices to receive posted read requests from one or more master devices. The sideband signals are used by the slave devices and associated arbitration logic to enable the slave devices with varying latencies to return requested data to the originating masters when the data becomes available. The sideband slave bus architecture may be applied to enhance performance of AMBA based bus architectures as well as other well-known bus architectures supporting one or more master devices.

Enhanced bus architecture for posted read operation between masters and slaves

A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

DEBUG mode for a data bus

A digital logic circuit, such as a FIFO memory, includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a &ldquo;2-hot&rdquo; encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding

A digital logic circuit, such as a FIFO memory includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a &ldquo;2-hot&rdquo; encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

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Boulder, CO, United States of America

David O Sluiter