Rambus Inc.

Super Talent Electronics, Inc.

Intel Corporation

David Nguyen

Ming-Shiang Shen

Jim Chin-Nan Ni

Craig Edward Hampel

Abraham C Ma

Frederick Abbott Ware

Richard Maurice Barth

Donald C Stark

Paul G Davis

James A Gasbarro

Abhijit Mukun Abhyankar

Nan Nan

Belgacem Haba

Haw-Jyh Liaw

Frank I-Kang Yu

Charles Chung Lee

Billy Wayne Garrett, Jr

I-Kang Yu

Donald Victor Perino

Thomas Francis Fox

Richard E Warmke

Xingchao C Yuan

Abraham Chih-Kang Ma

Sayeh Khalili

Ely K Tsern

Richard E Perego

Ravindranath T Kollipara

Suresh Rajan

Kyung Suk Oh

Frank Lambrecht

Jim C Ni

Richard DeWitt Crisp

Srinivas Nimmagadda

Wai-Yeung Yip

Andrew V Anderson

Peter D MacWilliams

David Q Chow

Thomas J Holman

Siew Sin Hiew

Paul Y Hsueh

Jin Kyu Kim

James A Gasborro

James A Gasbarre

Tsunwai Gary Yip

Crag E Hampel

Wai-Yeng Yip

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

Method and apparatus for indicating mask information

A USB plug receptacle includes a connector substrate having a tongue portion having a first set of electrical contact pins disposed on a top surface of the tongue portion, a second set of a plurality of electrical pins disposed on a bottom surface of the tongue portion, a third set of electrical contact pins disposed on an opposite end of the tongue portion. The USB plug receptacle further includes a metal case made of a sheet of electrically conductive metal plate by blanking the sheet into a generally tubular shape to receive and enclose the connector substrate. When the connector substrate is inserted into the metal case, the third set of electrical contact pins are exposed outside of the metal case and the third set of electrical contact pins can be mounted on first and second sets of electrical contact pads of a printed circuit board assembly.

Dual-personality extended USB plugs and receptacles using with PCBA and cable assembly

The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Stacked semiconductor module

A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.

Memory module having signal lines configured for sequential arrival of signals at a plurality of memory devices

An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

Extended USB plug, USB PCBA, and USB flash drive with dual-personality for embedded application with mother boards

An extended USB plug connector includes a connector substrate including a frontend having a first set of electrical contact pins disposed thereon and a backend having a second set of electrical contact pins disposed thereon. The first set includes a first row of electrical contact pins disposed on a top surface of the connector substrate and a second row of electrical contact pins disposed in parallel with the first row of electrical contact pins and interior to the first row of electrical contact pins, where the second row includes more electrical contact pins than the first row. The second set of electrical contact pins includes a number of electrical contact pins equal to the first row and second row of electrical contact pins in total. The second set of electrical contact pins are used to connect to corresponding electrical contact pads disposed on a printed circuit board assembly having a USB controller and flash memory devices disposed thereon.

A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.

Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices

A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Memory controller for controlling write signaling

In one embodiment of the present invention a Universal Serial Bus (USB) flash drive with locking swivel cap includes a USB device, a swivel cap having a top swivel cap face and a bottom swivel cap face. The swivel cap is connectably attached to the USB device, four locking pins, two of which disposed on the top swivel cap face and two of which disposed on the bottom swivel cap face, two top locking grooves disposed on a top surface of the USB device, and two bottom locking grooves disposed on a bottom surface of the USB device, wherein the locking pins disposed on top swivel cap face coupled with the two top locking grooves and the locking pins disposed on the bottom swivel cap face couple with the two bottom locking grooves allowing the swivel cap to lock in fully open (180 degrees) and fully closed (0 degree). A USB connector is connected to the USB device to couple the USB flash drive to a host device. A fingerprint sensor area is disposed on the top side of the USB device, the fingerprint sensor scans fingerprints of a user of the portable flash drive with swivel cap and optional fingerprint verification capability, and allowing access to data stored on the portable flash drive with swivel cap and optional fingerprint verification capability.

Universal serial bus (USB) flash drive having locking pins and locking grooves for locking swivel cap

A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data.

Multi-level cell (MLC) dual personality extended fiber optic flash memory device

The terminating module and method include integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

Clock routing in multiple channel modules and bus systems and method for routing the same

Extended USB plug, USB PCBA, and USB flash drive with dual-personality

In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Memory write signaling and methods thereof

Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter 'PLTPPUI') are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Memory address management systems in a large capacity multi-level cell (MLC) based flash memory device

Growing community of inventors

San Jose, CA, United States of America

David Nguyen