Altera Corporation

David Neto

Vaughn Betz

Ryan Fung

Meghal Varia

Jennifer Farrugia

Kumara Tharmalingam

Russell George Tessier

Thiagaraja Golpalsamy

Aaron Charles Egier

David Lewis

Michael David Hutton

Gregg William Baeckler

Deshanand Pratap Singh

David Karchmer

Ketan Padalia

Tomasz Czajkowski

Yi-Wen Lin

John Stuart Freeman

Mihail Iotov

David Ian M Milton

Pouyan Djahani

Elias Ahmed

Tian Yi David Han

Kimberley Anne Bozman

A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.

M/A for compiling parallel program having barrier synchronization for programmable hardware

A method for processing signals in a system includes deriving a signal activity for a signal from a timing requirement assignment for the signal.

Method and apparatus for deriving signal activities for power analysis and optimization

An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

Metastability-hardened synchronization circuit

A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.

Method and apparatus for protecting, optimizing, and reporting synchronizers

Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

Power-aware RAM processing

Systems and techniques are described for optimizing placement and routing by providing global information during early stages of a computer aided design (CAD) flow to produce better place and route solutions. Moreover, the systems and techniques described herein use natural connectivity information inherently provided in a design hierarchy.

Systems and methods for optimizing placement and routing

A method for managing simulation includes modifying a design for a system to allow for a path pulse filter to filter a pathpulse delay, on a signal transmitted to a component, that is greater than an IOpath delay.

Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in integrated circuits. Signals that toggle frequently are assigned to lower power multiplier ports or the number of times a signal changes value is minimized. Large width signals are assigned to the low power port. Large multipliers are divided up and optimized as above. Pipelined multipliers are used with registers so that signals change together.

Power reduction techniques for components in integrated circuits

During compilation of a user logic design in a first type of programmable logic device (e.g., an FPGA), a log is kept of at least certain steps where choices are made. When that logic design is migrated to another type of programmable logic device (e.g., a mask-programmable logic device) the logged steps are taken into account to make sure that the same choices are made, so that the target device is functionally equivalent to the original device.

Method and apparatus for compiling programmable logic device configurations

A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures.

A method for designing a system on a target device includes inserting sequential elements into combinatorial logic bounded by a source sequential element and a destination sequential element to reduce glitching. The sequential elements are clocked with a clock signal having a phase difference from at least one of a clock signal clocking the source sequential element and the destination sequential element.

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Toronto, Canada

David Neto