Texas Instruments Corporation

David N Walter

Mark Allen Gerber

Larry J Mowatt

Kurt Peter Wachtler

Duy-Loan T Le

Masood Murtuza

An improved semiconductor device package is manufactured by attaching semiconductor chips () on an insulating substrate () having contact pads (). A mold is provided, which has a top portion () with metal protrusions () at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.

Method for fabricating array-molded package-on-package

A semiconductor device with a sheet-like insulating substrate () integral with two or more patterned layers of conductive lines and vias, a chip attached to an assembly site, and contact pads () in pad locations has an encapsulated region on the top surface of the substrate, extending to the edge of the substrate, enclosing the chip, and having contact apertures () at the pad locations for external communication with the pad metal surfaces. The apertures may have not-smooth sidewall surfaces and may be filled with solder material () to contact the pads. Metal-filled surface grooves () in the encapsulated region, with smooth groove bottom and sidewalls, are selected to serve as customized routing interconnections, or redistribution lines, between selected apertures and thus to facilitate the coupling with another semiconductor device to form a package-on-package assembly.

Array-molded package-on-package having redistribution lines

Array molded package-on-package having redistribution lines

A device has a first semiconductor chip () with contact pads in an interior first set () and a peripheral second set (). A deformed sphere () of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere () is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate () with a chip attachment location and a third set of contact pads () near the location. Low profile bond wires () span between the pads of the third set and the second set. A second semiconductor chip () of a size has a fourth set of contact pads () at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal () bonds the spacers to the second chip, while the spacers space the first and second chips by a gap () wide enough for placing the wire spans to the second set pads.

Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices

The present invention comprises a low cost device ( ) and a method ( ) of forming an electrical interconnect between two metal substrate layers configured in a flip-chip format or a wire bonded format. The invention includes a first metal substrate layer ( ), a second metal substrate layer ( ), and an organic tape layer ( ) attached therebetween as a dielectric. The organic tape layer ( ) includes a series of spaced apart vias ( ) adapted to receive solder paste ( ). The second metal layer ( ) includes a plurality of openings ( ) spaced along the surface thereof and coaxially aligned with the spaced vias ( ). Further, the invention includes a plurality of solder balls ( ) placed across the respective openings ( ) of the second metal layer ( ) such that each solder ball ( ) attaches to the solder paste ( ) forming an electrical interconnect running substantially in parallel between the metal layers ( ). The solder balls are adapted to communicate I/O signals or power to/from an IC supported on the first layer.

Two-metal layer ball grid array and chip scale package having local interconnects used in wire-bonded and flip-chip semiconductor assembly

A high density interconnect device which creates a thin, electrically and thermally high performance package for semiconductor devices having a mechanically stable and high thermal conductivity substrate. Cavities in the substrate accommodate semiconductor devices attached directly to the substrate. The semiconductor devices include at least one optical receiver and/or transmitter. A thin film overlay having multiple layers interconnects the semiconductor devices to an array of pads on a surface of the thin film overlay facing away from the substrate. Connectors are attached to the pads to provide direct electrical and mechanical attachment to other system hardware. In one embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through holes formed through the thin film overlay. The holes may be back filled with an optical quality material.

HID land grid array packaged device having electrical and optical interconnects

A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer ( ) having a hole ( ) disposed therein for receiving an integrated circuit chip die ( ). A lower core laminate layer ( ) having a conductive layer ( ) and conductive layer ( ) disposed on opposite sides thereof is laminated to the lower surface of the layer ( ). Plated-through holes ( ), ( ) and ( ) are formed through the two layers ( ) and ( ) to connect the conductive layer ( ) with a conductive layer ( ) on the upper surface of the layer ( ). A high-density interconnect layer includes two laminate layers ( ) and ( ), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer ( ) allow for connections from the die ( ) to the conductive layer ( ). The via interconnect structures formed in the layer ( ) allow interconnection from the upper surface of layer ( ) to via interconnects formed in the layer ( ). An I/O connector is interfaced with select ones of the plated-through holes with pins ( ) and ( ). This allows an interface from the module to an operating system through pins ( ).

Multi-chip integrated circuit module

A high density interconnect land grid array package device combines various electronic packaging techniques in a unique way to create a very thin, electrically and thermally high performance package for single or multiple semiconductor devices. A thin and mechanically stable substrate or packaging material (,) is selected that also has high thermal conductivity. Cavities (,) in the substrate or packaging material (,) accommodate one or more semiconductor devices that are attached directly to the substrate or packaging material. At least one of said semiconductor devices includes at least one optical receiver and/or transmitter. A thin film overlay (,) having multiple layers interconnects the one or more semiconductor devices to an array of pads (,) on a surface of the thin film overlay facing away from the substrate or packaging material. Solder balls (,), conductive adhesive or elastomeric connectors are attached to the pads to provide direct electrical and mechanical attachment means to other system hardware. In one embodiment of the invention, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment of the invention, the optical receiver and/or transmitter receives and/or transmits light signals through holes (,) formed through the thin film overlay. The holes may be back filled with an optical quality material.

HDI land grid array packaged device having electrical and optical interconnects

A multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).

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Dallas, TX, United States of America

David N Walter