Intel Corporation

Velanidi Technologies LLC

David N Shykind

James A McCall

Manish Chandhok

Charles Henry Wallace

Paul Anton Nyhus

Eungnak Han

Gurpreet Singh

Florian Gstrein

Devin Thomas Wiley

Jinnie Aloysius

Jane Ni

Noriyuki Sato

Kevin Lai Lin

Leonard P Guler

Hui Jae Yoo

Richard E Schenker

Yan A Borodovsky

Mohit K Haran

Travis M Eiles

Klaus J Ruff

Sean Michael Pursel

Gobind Bisht

Jonathan Laib

Markus Kuhn

Nafees Kabir

Jose A Maiz

Santanu Chaudhuri

Todd R Younkin

Nityan Labros Nair

Brandon Jay Holybee

Xuanxuan Chen

John Burghard

Chris Kenyon

Thomas Christopher Hoff

Rajiv Giridharagopal

Carmen Campbell

Cameron Wagner

Steven M Stahlberg

James Mccall

Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

Directed self-assembly enabled patterning over metal layers using assisting features

Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.

Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication

A method of using a device to detect a target entity in an environment includes introducing the device into the environment. The device includes first and second conductive surfaces, with a first molecular wire electrically coupling the first conductive surface to a capture agent that can interact with the target entity, and a second molecular wire electrically coupling the second conductive surface to a reference compound. The first and the second molecular wires comprise oligonucleotide multiplexes having identical nucleobase sequences and opposite absolute configuration. The method also includes detecting, by the device, an interaction between the capture agent and the target entity, at least in part by amplifying a differential voltage between the first and second conductive surfaces and detecting the interaction based on the differential voltage.

Molecular wires for detecting a biological or chemical entity or event

An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

Self aligned gratings for tight pitch interconnects and methods of fabrication

Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

Gate spacing in integrated circuit structures

A method of fabricating a device includes fabricating conductive surfaces including one or more capture surfaces and one or more reference surfaces, attaching a first molecular wire to each capture surface, and attaching a second molecular wire to each reference surface. The first and second molecular wires include chiral oligonucleotide multiplexes having identical nucleobase sequences and opposite absolute configuration. The first molecular wire includes a first oligonucleotide strand conjugated to a first functional handle including a sulfur-containing compound, and a second oligonucleotide strand conjugated to a capture agent that interacts with a target entity. The second molecular wire includes a first oligonucleotide strand conjugated to a second functional handle including a sulfur-containing compound, and a second oligonucleotide strand conjugated to a reference compound. The first and second oligonucleotide strands of each molecular wire are complementary and have the same absolute configuration.

An apparatus that is μm- or nm-scale in size and can include integrated circuitry logic based on sub 10 nm SIA transistor nodes, a sensing subsystem, a deciding subsystem, an effecting subsystem, and a power harvesting system is described. The sensing subsystem can identify pathogenic entities, including disease associated cells (for example, cancer cells, autoimmune cells, or pathological microbes) or viruses. The sensing subsystem can include at least one pad constructed of an electrically conductive material and linkers attached to the at least one pad. Each linker can also be attached to a targeting agent (for example, an antibody fragment) or a reference agent. Upon the binding of a targeting agent with an entity of interest, the information is transferred to the logic circuitry, which processes the binding event information and decides whether the entity is disease associated (e.g., a disease associated cell or virus) and requires delivery of therapeutic agents or other treatment.

System, apparatus and method for sensing, detecting and effecting in a micro-to-nano environment

Enantiomeric pairs of molecular wires comprised of oligomeric nucleic acids, wherein the oligomers of each wire possess identical nucleobase pair sequences and thus identical conductivity as between wires, are constructed and used to sense biological or chemical entities of interest at the cellular or molecular level. The oligomeric molecular wires conduct voltage inputs to sensing subsystem integrated circuitry, either from an electrostatic potential arising from a targeting agent (i.e., a capture agent) binding to an intended biological or chemical target molecule, or from an electrostatic potential associated with a reference molecule that has non-specific interactions with the environment. The chirality of the oligomers imparts selectivity to either the targeting agent or the reference molecule during assembly of the sensing subsystem.

Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens positioned in front of the laser to focus the laser beam on an active region of an integrated circuit through a back side of an integrated circuit die, and a detector positioned to receive a reflected laser beam reflected from the active region through a back side of the die, through the objective lens. The detector is configured to detect an amplitude modulation of the reflected laser beam wherein the amplitude modulation is attributable to the electric field at the active region.

Visible laser probing for circuit debug and defect analysis

A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.

Method of manufacturing a circuit board

A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Method of creating a maskless air gap in back end interconnections with double self-aligned vias

A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Adaptive delay base loss equalization

Method of creating a maskless air gap in back end interconnects with double self-aligned vias

Growing community of inventors

Sherwood, OR, United States of America

David N Shykind