Motorola Corporation

Other

David N Okada

Michael P Masquelier

Robert Bruce Davies

James W Holm-Kennedy

Lowell E Clark

A method for forming a plurality of surface conduction paths (33) in a conductive region (16) of a first conductivity type. A plurality of areas (17) of a second conductivity type are formed in the conductive region (16). The plurality of areas (17) deplete the conductive region (16) when a reverse bias voltage is placed across the conductive region (16) and the plurality of areas (17). Area of the conductive region (16) adjacent to each of the plurality of areas (17) form the plurality of surface conduction paths (33) for conducting current through the conductive region (16).

High voltage transistor having reduced on-resistance

A method of internally limiting current and providing overvoltage protection in a semiconductor device comprises providing a semiconductor device having at least a first junction wherein both sides of the junction have predetermined dopant concentrations and wherein the first junction is spaced apart a predetermined distance from either a second junction or current blocking means. The predetermined dopant concentrations and distance are such that when a predetermined voltage is applied to the device, a depletion region from the first junction encounters either a depletion region from the second junction or current blocking means, thereby pinching off current at a desired voltage. The pinch-off voltage may be varied by adjusting the distance between the first junction and either the second junction or current blocking means and also by adjusting the predetermined dopant concentrations.

Internal current limit and overvoltage protection method

A high voltage semiconductor structure having multiple guard rings, wherein guard rings farthest from a main junction are spaced further from each other than are guard rings closer to the main junction is provided. An enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings, thereby increasing the breakdown voltage of the device. The enhancement region and close guard ring spacing result in a fine gradation of electric field and high punch-through breakdown voltage between guard rings.

High voltage planar edge termination using a punch-through retarding

A method of fabricating a lateral semiconductor structure includes providing a semiconductor substrate and forming wells therein. Following formation of a dielectric layer on the substrate, field region openings are formed through which field regions are implanted into the substrate. The self-aligned formation of field oxidation regions to the field region openings then occurs and is followed by the formation of field plates on the field oxidation regions. A first active device region is then formed in said substrate, the formation of which is self-aligned to the field plates. This is followed by the formation of a second active device region in the first active device region which is also self-aligned to the field plates. The resulting structure allows for high speed devices that maintain consistently high current gain without sacrificing Early or breakdown voltages.

Method of fabricating a lateral semiconductor structure including field

A merged channel and bipolar device which exploits the distributed character of the device generates useful electronic characteristics by controlling the current and voltage inputs to the four or more terminals attached to the device, said electronic characteristics being useful for affecting the ac and dc current gain of the device, its transconductance, non-linearities, the electronic output characteristics as a function of input signals, electronic switching, gain control, output limiting, heterodyning, harmonic generation and voltage references. Other applications which employ non-linear behavior include distributed amplification of traveling waves, multiple methods for chemical sensing and other sensor applications. The device behavior can be strongly affected by the device's distributed nature with bipolar behavior and FET behavior substantially different in different regions of the device, and the onset and distribution of this heterogenious behavior being affected directly by the input electrical voltages and currents. Channel geometry and conductivity and gate shape (where a gate is employed) can be used to affect the desired electrical performance. Sensing applications can be affected by intentional modification of surface parameters such as surface recombination, velocity, and by choice of gate materials and gate shape where a gate is used. Applications of the device encompass electrical parameter generation useful for circuit applications. An example is the generation of an accurate reference voltage V.sub.thg and constant current values, and transducing and sensing applications for sensing chemicals, magnetic fields, forces, pressure, and other tranducing stimuli.

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Tempe, AZ, United States of America

David N Okada