Intel Corporation

David N Lombard

Jonathan M Eastep

Richard J Greco

Ilya Sharapov

Phani Kumar Kandula

Hari K Nagpal

Ricardo A Morin

Rohit Banerjee

Rodolfo Kohn

Steve S Sylvester

Mark J Luckeroth

Arzhan I Kinzhalin

Brad Bittel

John Kelbert

Nikos Kaburlasos

Mallik Bulusu

Robert Charles Swanson

Amit Kumar Srivastava

Keith D Underwood

Narayan Ranganathan

Malay Trivedi

Robert Bruce Bahnsen

Janusz Jurski

James Mitchell

Chih-Cheh Chen

Eric J Moret

Piotr Michael Kwidzinski

Steffen Kosinski

Eric J M Moret

Rob F Van Der Wijngaart

Jan Uerpmann

Marc Beuchat

Rodrigo De Oliveira Vivi

Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices

Methods, apparatus, systems, and articles of manufacture to reduce thermal fluctuations in semiconductor processors are disclosed. An apparatus includes a temperature analyzer to determine a current temperature of a processor. The apparatus further includes a controller to provide an idle workload to the processor to execute in response to the current temperature falling below a setback temperature.

Methods and apparatus to reduce thermal fluctuations in semiconductor processors

An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.

Dynamic lane access switching between PCIe root spaces

Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.

Systems and methods for dynamic spatial power steering

Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.

Dynamic hierarchical performance balancing of computational resources

A method and device for managing hardware errors in a multi-core environment includes allocating processor cores to a main set and a spare set of processor cores. The main set of processor cores are used by an operating system, and the spare set of processor cores are dedicated to software applications. Should a processor core error occur, a processor core swap may be performed to swap a spare processor core for a failing main processor core without interrupting the execution of the operating system.

Method and device for managing hardware errors in a multi-core environment

Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.

Progress meters in parallel computing

An embodiment may include network controller circuitry to be included in a first host computer that includes a host processor to execute an operating system environment. The circuitry may initiate, at least in part, one or more checkpoints of, at least in part, one or more states associated with, at least in part, the operating system environment and network traffic between the first host computer and a second host computer. The circuitry also may coordinate, at least in part, respective execution, at least in part, of the one or more checkpoints with respective execution of one or more other respective checkpoints of the second host computer. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Network controller circuitry to initiate, at least in part, one or more checkpoints

In one embodiment, the present invention includes a method for initializing a common information model (CIM) broker and a SLP service agent of a system in a pre-boot environment, transmitting a multicast request and receiving a unicast advertisement from a directory agent, registering a web-based enterprise management (WBEM) service to the directory agent, and configuring, provisioning, and/or performing asset inventory of the system in the pre-boot environment responsive to information from a resource manager. Other embodiments are described and claimed.

Platform discovery, asset inventory, configuration, and provisioning in a pre-boot environment using web services

Growing community of inventors

Rossmoor, CA, United States of America

David N Lombard