International Business Machines Corporation

David N Gooding

Everett M Shimp

Stefan P Jackowski

James T Moyer

James W Plant

A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.

Failure detection method and apparatus

A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values. The input modifier circuitry for one of the numbers also includes circuitry for increasing the value of each digit in such number by a factor of six for enabling the proper generation of digit carries inside the binary adder. The output corrector includes circuitry for reducing, when necessary, the value of one or more of the output digits by a factor of six to offset the increase in the input digits. Subtraction is accomplished by complementing one of the numbers before it is supplied to the binary adder. Sign handling circuitry detects the polarities or signs of the two input numbers as well as the status of an external add/subtract command and processes these three factors to develop a control signal for controlling the use of the complementing action for enabling the number appearing at the output of the output corrector to be in true magnitude form whenever possible. The input modifier circuitry, the output corrector and the sign handling circuitry are constructed so that packed binary coded decimal numbers and pure binary numbers can also be handled by the arithmetic unit.

Arithmetic unit for a digital data processor

Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor. In such case, the current storage address and a requested storage access length value are supplied to the first arithmetic unit zone for producing a new address representing the upper extent of the storage access request. The resultant new address is immediately supplied back to the input of the second arithmetic unit zone for combining same with an upper limit address for immediately producing an upper bounds extent error when the new address exceeds the upper limit address.

Upper bounds address checking system for providing storage protection

A carry look-ahead parallel digital adder having a relatively wide overall data flow width and a pair of automatically adjustable boundary mechanisms for subdividing the adder into plural independent operating zones of variable width and variable location. Anywhere from one to three independent zones may be obtained. Independent external carry-in and carry-out lines are provided for each zone and the connecting points for such lines are automatically shifted in step with the movement of the zone boundaries.

Parallel digital arithmetic device having a variable number of

A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

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Endicott, NY, United States of America

David N Gooding