Netapp, Inc.

David Morgan Robles

Joshua Oren Silberman

George Totolos, Jr

William McGovern

Wayne Ando

Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Power management techniques for computer-readable storage devices

A system and method for prioritized queues is provided. A plurality of queues are organized to enable long-running operations to be directed to a long running queue operation, while faster operations are directed to a non-long running operation queue. When an operation request is received, a determination is made whether it is a long-running operation, and, if so, the operation is placed in a long-running operation queue. When the processor core that is executing long-running operations is ready for the next operation, it removes an operation from the long-running operation queue and processes the operation.

System having operation queues corresponding to operation execution time

Method and system are provided for handling data when power failure from a primary power source of a storage system is detected. The system provides a first memory and a second memory. The first memory is primarily used to store data when the primary power source is operating. If a power failure is detected, a first indicator is set to indicate that data is stored or being transferred to the second memory. Thereafter, data is transferred from the first memory to the second memory. Any errors during the transfer are logged. Once power is restored, data is transferred back to the first memory. A second indicator is set to indicate that there is no data at the second memory.

Redundant memory system and associated method thereof

A system and method enables efficient transfer and cryptographic processing of data within a security appliance. A network adapter of the security appliance initiates a random access data transfer to a system memory that is illustratively organized into a plurality of blocks of predetermined size. Mapping circuitry of the appliance is configured to track the progress of the data transfer between the adapter and memory such that, once data is stored in a memory block, an encryption processor of the appliance may process the data or the network adapter may retrieve the processed data without having to wait for completion of the data transfer between the adapter and memory, thereby reducing processing latency in the security appliance.

System and method for reducing processing latency in a security appliance

A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processor is configured to execute, a corresponding interrupt controller is provided. To switch the processor to a task, the corresponding interrupt controller signals the root interrupt controller which, in turn, sends an interrupt and a Task Identifier to the processor. The root interrupt controller also cooperates with an access multiplexer/demultiplexer to select the corresponding interrupt controller for communication with the processor. By providing interrupt controller selection as well as task identification, the hierarchical array offloads arbitration and context switching overhead from the processor. That is, in response to the interrupt, the processor switches to the identified task and may access a memory address space dedicated to the task.

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Alameda, CA, United States of America

David Morgan Robles