Stmicroelectronics Gmbh

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

David Moreau

Kangguo Cheng

Ruilong Xie

Bruce Bennett Doris

Tenko Yamashita

Ajey Poovannummoottil Jacob

Xiuyu Cai

Su Chen Fan

Kisik Choi

Muthumanickam Sankarapandian

Pierre Morin

Murat Kerem Akarvardar

Jason Cantone

Susan S Fan

Sylvie M Mignot

Dongseok Lee

Jerome Ciavatti

A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.

Fin formation for semiconductor device

A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Method for single fin cuts using selective ion implants

A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.

Extended liner for localized thick copper interconnect

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Pflugerville, TX, United States of America

David Moreau