Sigmatel, Inc.

David Moore

Matthew Brady Henson

Russell Alvin Schultz

Marc Kevin Jordan

A method for booting a system on a chip (IC) integrated circuit includes reading a warm boot flag stored in a persistent register of an analog portion of the system on a chip IC. A warm boot procedure is executed when the warm boot flag is set.

Method for booting a system on a chip integrated circuit

The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is configured to access a virtual memory space to perform a first task and is configured to access the virtual memory space to perform a second task. The virtual memory space references first and second sets of task instructions associated with the first and second tasks, respectively. The virtual memory space references non-instruction data associated with the first task. The cache memory is configured to store the first set of task instructions and the non-instruction data. The memory management unit is configured to determine the physical memory location of the second set of task instructions. The computational system is configured to not write the first set of task instructions and the non-instruction data to a physical location beyond the cache memory.

Method and system of memory management

The disclosure is directed to a computational system including a processor and a memory management unit accessible to the processor. The processor is configured to access a common virtual memory space to perform a first task of a plurality of tasks and is configured to access the common virtual memory space to perform a second task of the plurality of tasks. The common virtual memory space references a first set of instructions associated with the first task and references a second set of instructions associated with the second task. The memory management unit is configured to determine a physical memory location of at least one of the first and second sets of instructions when the associated first or second task is to be performed by the processor.

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Cedar Park, TX, United States of America

David Moore