Koninklijke Philips Corporation N.V.

David Modrie

Aalbert Stek

Rob Otte

Koen Vanhoof

Jo Stefan Frisson

Willem Marie Coene

A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means () for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means () for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter () converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator () for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means () for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector () for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means () are controlled by a preset value for keeping the ratio T/Ts constant.

Semi-synchronous receiver and apparatus for reading information

The invention relates to an LMS-based asynchronous receiver for digital transmission and recording systems. The receiver comprises a digital adaptive equalizer (EQ) for receiving a received sequence rn and for delivering an equalized sequence yn. The equalizer (EQ) operates at the sampling rate 1/Ts, asynchronous to the data rate 1/T. An equalizer adaptation method using LMS techniques is described for adapting equalizer taps asynchronously to the data rate via a control loop. A first sampling rate converter (SRC) performs timing recovery at the data rate 1/T after equalization on the equalized sequence yn. A second sampling rate converter (SRC) is provided for converting a delayed version of the received sequence rn into an intermediate control sequence ik at the data rate 1/T.

Adaptive equalizer operating at a sampling rate asynchronous to the data rate

A device for delivering a data signal at a data rate has crosstalk cancellation. The crosstalk reducing unit () has an adaptive filter () to generate a crosstalk signal corresponding to a track adjacent to a track being scanned. A subtractor () subtracts the crosstalk signal from a read signal. A calculating unit () calculates filter coefficients for the adaptive filter. The adaptive filter () and subtractor () are coupled to an asynchronous clock () for operating at an asynchronous sample rate. The crosstalk reducing unit () has a sample rate converter () coupled to a synchronous clock for converting the output of the subtractor to the data signal () at a synchronous sample rate. A timing recovery unit () is coupled to the data signal () for retrieving the synchronous clock corresponding to the data rate. This has the advantage that the latency introduced by the crosstalk cancellation processing doesn't contribute to the overall delay of the timing recovery loop, while the latter still profits from the crosstalk cancellation.

Asynchronous crosstalk cancellation

The invention relates to an interference-free LMS-based asynchronous receiver for digital transmission and recording systems. The receiver, having an asynchronously placed LMS-based adaptive equalizer, has 2 control loops: a timing recovery loop (by means of, for instance a PLL (Phase locked loop) and an equalizer's adaptation loop. Interference between the two loops is avoided by deriving a condition the equalizer should fulfill to avoid the interference between the two loops, which implies 'orthogonal control functionality' and by combining the condition with the equalizer's adaptation loop. The equalizer shall adapt so that the condition is always true.

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Leuven, Belgium

David Modrie